ST STM32H7 3 Series User Manual

DocID029918 Rev 1 23/48
AN4938 Boot configuration
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4 Boot configuration
4.1 Boot mode selection
In STM32H743/753xx microcontrollers, two different boot spaces can be selected through
the BOOT pin and the boot base address programmed in the BOOT_ADD0 or BOOT_ADD1
option bytes as shown in the
Table 1.
The BOOT_ADD0 and BOOT_ADD1 address option bytes allow to program any boot
memory address from 0x0000
0000 to 0x3FFF 0000 which include:
• All the Flash memory address space mapped on AXIM interface.
• All the RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM
interface.
• The system memory bootloader.
The BOOT_ADD0/BOOT_ADD1 option bytes can be modified after the reset in order to
boot from any other boot address after the next reset.
If the programmed boot memory address is out of the memory mapped area or a reserved
area, the default boot fetch address is programmed as follows:
• Boot address 0: Flash memory at 0x0800 0000
• Boot address 1: ITCM-RAM at 0x0000 0000
When the Flash level 2 protection is enabled, only boot from Flash memory is available. If
the boot address already programmed in the BOOT_ADD0 / BOOT_ADD1 option bytes is
out of the memory range or belongs to the RAM address range, the default fetch will be
forced from Flash memory at address 0x0800 0000.
Note: When the Secure access mode is enabled through option bytes, the boot behavior differs
from the above description (refer to section Root secure services of the product reference
manual).
Table 1. Boot modes
Boot mode selection
Boot space
BOOT
pin
Boot address
option bytes
0 BOOT_ADD0 [15:0]
Boot address defined by BOOT_ADD0[15:0] user option byte
Default factory programmed value: User Flash memory starting at
0x0800 0000
1 BOOT_ADD1 [15:0]
Boot address defined by BOOT_ADD1[15:0] user option byte
Default factory programmed value: System Flash memory starting
at 0x1FF0 0000

ST STM32H7 3 Series Specifications

General

Brand	ST
Model	STM32H7 3 Series
Category	Microcontrollers
Language	English

Summary

Introduction to STM32H7 Hardware Development

Hardware Features Overview

Overview of power supply, clock, reset, boot modes, and debug features.

Minimum Hardware Resources

Specifies the essential hardware components for STM32H7x3 development.

Power Supplies for STM32H7 Microcontrollers

Power Supply Overview

Details on VDD, analog, USB, and backup power supplies.

Independent Analog Supply and Reference

VDDA, VSSA, VREF+ for analog peripherals, accuracy.

USB Transceiver Power Supply

VDD33USB and VDD50USB for USB transceivers, voltage ranges.

Battery Backup Domain (VBAT)

Powering RTC, backup registers, and SRAM when VDD is off.

LDO Voltage Regulator

Core voltage regulation, VOS levels, and VCAP requirements.

Power Supply Scheme and Decoupling

External Power Supply Connections

VDD, VDDA, VDD33USB/VDD50USB connections and decoupling caps.

VBAT, VREF+, VDDLDO Connections

VBAT, VREF+ for analog, and VDDLDO connections with VCAPs.

Reset and Power Supply Supervisor Features

Power-On/Power-Down Reset (POR/PDR)

Integrated POR/PDR for reliable operation starting from 1.71 V.

Programmable Voltage Detector (PVD)

Monitors VDD against a threshold, triggers interrupts on voltage changes.

Analog Voltage Detector (AVD)

Monitors VDDA against a threshold, triggers interrupts.

System Reset Sources

Events triggering system reset (NRST, watchdog, software).

Internal Reset Control (PDR_ON)

Using PDR_ON pin to enable/disable internal reset functionalities.

Bypass Mode Operation

Bypassing power management unit, core supply via VCAPx.

Alternate Function Mapping to Pins

Using STM32CubeMX for Pin Mapping

Recommends STM32CubeMX tool for exploring peripheral pin assignments.

Clock Management and Oscillators

System and Secondary Clock Sources

HSI, CSI, HSE, PLL, LSI, LSE clock sources for the microcontroller.

HSE Oscillator Clock Configuration

Using external clock or crystal/ceramic resonator for HSE.

LSE Oscillator Clock Configuration

Using external clock or crystal/ceramic resonator for LSE.

Clock Security System (CSS)

HSE and LSE Clock Failure Detection

CSS for HSE and LSE to detect failures and switch sources.

Boot Configuration Options

Boot Mode Selection

Selecting boot space via BOOT pin and option bytes.

System Bootloader Mode

Embedded bootloader for Flash programming via serial interfaces.

Debugging and Trace Interfaces

Host-Target Debug Connection

Components for connecting host PC to the evaluation board for debugging.

SWJ Debug Port (Serial Wire/JTAG)

ARM CoreSight SWJ-DP for combined JTAG and SW debugging.

TPIU Trace Port

Trace port for capturing execution data, 4 data lines + clock.

External Debug Trigger Pins

TRGIN/TRGOUT or TRGIO pins for external debug triggering.

SWJ Debug Port Pin Assignments

Detailed pin assignments for SWJ-DP functionality.

Flexible SWJ-DP Pin Assignment

Releasing SWJ-DP pins for general-purpose I/O usage.

JTAG Pin Configuration

Internal pull-up/pull-down resistors on JTAG pins.

SWJ Connection to JTAG Connector

Wiring the SWJ debug port to a standard JTAG connector.

Design and PCB Recommendations

Printed Circuit Board (PCB) Design

Using multilayer PCBs with dedicated ground/power planes.

Component Placement and Grounding

Strategic component placement and proper grounding for EMI reduction.

Power Supply Decoupling

Using decoupling capacitors close to MCU pins for noise reduction.

Managing Other Signals and Unused Features

Optimizing EMC by studying signals and configuring unused resources.

Reference Design Components and Setup

Reference Design Description

Overview of the STM32H753XI based reference design.

Clock Configuration in Reference Design

LSE and HSE crystal usage for RTC and main clock.

Reset and Power Supply in Reference Design

Reset sources and power supply connections for the reference design.

Boot Mode and SWJ Interface

References to boot config and debug sections.

Mandatory and Optional Components

Lists of essential and optional components for the reference design.

Reference Pin Connections for STM32H7 Packages

Recommended PCB Routing Guidelines

PCB Stack-up Design

Choosing stack-ups for signal integrity and impedance matching.

Crystal Oscillator and Power Decoupling Layout

Guidelines for crystal oscillator layout and power supply decoupling.

High Speed Signal Layout Guidelines

SDMMC, FMC, QUADSPI Interface Layout

Signal layout for SDMMC, FMC, and QUADSPI interfaces.

Embedded Trace Macrocell (ETM) Interface Layout

Signal layout guidelines for the ETM interface.

Conclusion and Application Note Usage

Document Revision History