Recommended PCB routing guidelines for STM32H743/753xx devices AN4938
42/48 DocID029918 Rev 1
8.4 High speed signal layout
8.4.1 SDMMC bus interface
Interface connectivity
The SD/SDIO MMC card host interface (SDMMC) provides an interface between the AHB
peripheral bus and Multi Media Cards (MMCs), SD memory cards and SDIO cards. The
SDMMC interface is a serial data bus interface, that consists of a clock (CK), command
signal (CMD) and 8 data lines (D[0:7]).
Interface signal layout guidelines
• Reference the plane using GND or PWR (if PWR, add 10nf switching cap between
PWR and GND)
• Trace the impedance: 50 Ω ± 10%
• The skew being introduced into the clock system by unequal trace lengths and loads,
minimize the board skew, keep the trace lengths equal between the data and clock.
• The maximum skew between data and clock should be below 250 ps @ 10mm
• The maximum trace length should be below 120 mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
• The trace capacitance should not exceed 20 pF at 3.3 V and 15 pF at 1.8 V
• The maximum signal trace inductance should be less than 16 nH
• Use the recommended pull-up resistance for CMD and data signals to prevent bus
floating.
• The mismatch within data bus, data and CK or CK and CMD should be below 10mm.
• Keep the same number of vias between the data signals
Note: The total capacitance of the SD memory card bus is the sum of the bus master capacitance
C
HOST
, the bus capacitance C
BUS
itself and the capacitance C
CARD
of each card connected
to this line. The total bus capacitance is C
L
= C
Host
+ C
Bus
+ N*C
Card
where the host is an
STM32H743/753xx device, bus is all the signals and Card is SD card.
8.4.2 Flexible memory controller (FMC) interface
Interface connectivity
The FMC controller and in particular SDRAM memory controller which has many signals,
most of them have a similar functionality and work together. The controller I/O signals could
be split in four groups as follow:
• An address group which consists of row/column address and bank address
• A command group which includes the row address strobe (NRAS), the column address
strobe (NCAS), and the write enable (SDWE)
• A control group which includes a chip select bank1 and bank2 (SDNE0/1), a clock
enable bank1 and bank2 (SDCKE0/1), and an output byte mask for the write access
(DQM).
• A data group/lane which contains 8 signals
(a)
: the eight D (D7–D0) and the data mask
(DQM).
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