ST STM32H7 3 Series User Manual

Recommended PCB routing guidelines for STM32H743/753xx devices AN4938
42/48 DocID029918 Rev 1
8.4 High speed signal layout
8.4.1 SDMMC bus interface
Interface connectivity
The SD/SDIO MMC card host interface (SDMMC) provides an interface between the AHB
peripheral bus and Multi Media Cards (MMCs), SD memory cards and SDIO cards. The
SDMMC interface is a serial data bus interface, that consists of a clock (CK), command
signal (CMD) and 8 data lines (D[0:7]).
Interface signal layout guidelines
• Reference the plane using GND or PWR (if PWR, add 10nf switching cap between
PWR and GND)
• Trace the impedance: 50 Ω ± 10%
• The skew being introduced into the clock system by unequal trace lengths and loads,
minimize the board skew, keep the trace lengths equal between the data and clock.
• The maximum skew between data and clock should be below 250 ps @ 10mm
• The maximum trace length should be below 120 mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
• The trace capacitance should not exceed 20 pF at 3.3 V and 15 pF at 1.8 V
• The maximum signal trace inductance should be less than 16 nH
• Use the recommended pull-up resistance for CMD and data signals to prevent bus
floating.
• The mismatch within data bus, data and CK or CK and CMD should be below 10mm.
• Keep the same number of vias between the data signals
Note: The total capacitance of the SD memory card bus is the sum of the bus master capacitance
C
HOST
, the bus capacitance C
BUS
itself and the capacitance C
CARD
of each card connected
to this line. The total bus capacitance is C
L
= C
Host
+ C
Bus
+ N*C
Card
where the host is an
STM32H743/753xx device, bus is all the signals and Card is SD card.
8.4.2 Flexible memory controller (FMC) interface
Interface connectivity
The FMC controller and in particular SDRAM memory controller which has many signals,
most of them have a similar functionality and work together. The controller I/O signals could
be split in four groups as follow:
• An address group which consists of row/column address and bank address
• A command group which includes the row address strobe (NRAS), the column address
strobe (NCAS), and the write enable (SDWE)
• A control group which includes a chip select bank1 and bank2 (SDNE0/1), a clock
enable bank1 and bank2 (SDCKE0/1), and an output byte mask for the write access
(DQM).
• A data group/lane which contains 8 signals
(a)
: the eight D (D7–D0) and the data mask
(DQM).

ST STM32H7 3 Series Specifications

General

Brand	ST
Model	STM32H7 3 Series
Category	Microcontrollers
Language	English

Summary

Introduction to STM32H7 Hardware Development

Hardware Features Overview

Overview of power supply, clock, reset, boot modes, and debug features.

Minimum Hardware Resources

Specifies the essential hardware components for STM32H7x3 development.

Power Supplies for STM32H7 Microcontrollers

Power Supply Overview

Details on VDD, analog, USB, and backup power supplies.

Independent Analog Supply and Reference

VDDA, VSSA, VREF+ for analog peripherals, accuracy.

USB Transceiver Power Supply

VDD33USB and VDD50USB for USB transceivers, voltage ranges.

Battery Backup Domain (VBAT)

Powering RTC, backup registers, and SRAM when VDD is off.

LDO Voltage Regulator

Core voltage regulation, VOS levels, and VCAP requirements.

Power Supply Scheme and Decoupling

External Power Supply Connections

VDD, VDDA, VDD33USB/VDD50USB connections and decoupling caps.

VBAT, VREF+, VDDLDO Connections

VBAT, VREF+ for analog, and VDDLDO connections with VCAPs.

Reset and Power Supply Supervisor Features

Power-On/Power-Down Reset (POR/PDR)

Integrated POR/PDR for reliable operation starting from 1.71 V.

Programmable Voltage Detector (PVD)

Monitors VDD against a threshold, triggers interrupts on voltage changes.

Analog Voltage Detector (AVD)

Monitors VDDA against a threshold, triggers interrupts.

System Reset Sources

Events triggering system reset (NRST, watchdog, software).

Internal Reset Control (PDR_ON)

Using PDR_ON pin to enable/disable internal reset functionalities.

Bypass Mode Operation

Bypassing power management unit, core supply via VCAPx.

Alternate Function Mapping to Pins

Using STM32CubeMX for Pin Mapping

Recommends STM32CubeMX tool for exploring peripheral pin assignments.

Clock Management and Oscillators

System and Secondary Clock Sources

HSI, CSI, HSE, PLL, LSI, LSE clock sources for the microcontroller.

HSE Oscillator Clock Configuration

Using external clock or crystal/ceramic resonator for HSE.

LSE Oscillator Clock Configuration

Using external clock or crystal/ceramic resonator for LSE.

Clock Security System (CSS)

HSE and LSE Clock Failure Detection

CSS for HSE and LSE to detect failures and switch sources.

Boot Configuration Options

Boot Mode Selection

Selecting boot space via BOOT pin and option bytes.

System Bootloader Mode

Embedded bootloader for Flash programming via serial interfaces.

Debugging and Trace Interfaces

Host-Target Debug Connection

Components for connecting host PC to the evaluation board for debugging.

SWJ Debug Port (Serial Wire/JTAG)

ARM CoreSight SWJ-DP for combined JTAG and SW debugging.

TPIU Trace Port

Trace port for capturing execution data, 4 data lines + clock.

External Debug Trigger Pins

TRGIN/TRGOUT or TRGIO pins for external debug triggering.

SWJ Debug Port Pin Assignments

Detailed pin assignments for SWJ-DP functionality.

Flexible SWJ-DP Pin Assignment

Releasing SWJ-DP pins for general-purpose I/O usage.

JTAG Pin Configuration

Internal pull-up/pull-down resistors on JTAG pins.

SWJ Connection to JTAG Connector

Wiring the SWJ debug port to a standard JTAG connector.

Design and PCB Recommendations

Printed Circuit Board (PCB) Design

Using multilayer PCBs with dedicated ground/power planes.

Component Placement and Grounding

Strategic component placement and proper grounding for EMI reduction.

Power Supply Decoupling

Using decoupling capacitors close to MCU pins for noise reduction.

Managing Other Signals and Unused Features

Optimizing EMC by studying signals and configuring unused resources.

Reference Design Components and Setup

Reference Design Description

Overview of the STM32H753XI based reference design.

Clock Configuration in Reference Design

LSE and HSE crystal usage for RTC and main clock.

Reset and Power Supply in Reference Design

Reset sources and power supply connections for the reference design.

Boot Mode and SWJ Interface

References to boot config and debug sections.

Mandatory and Optional Components

Lists of essential and optional components for the reference design.

Reference Pin Connections for STM32H7 Packages

Recommended PCB Routing Guidelines

PCB Stack-up Design

Choosing stack-ups for signal integrity and impedance matching.

Crystal Oscillator and Power Decoupling Layout

Guidelines for crystal oscillator layout and power supply decoupling.

High Speed Signal Layout Guidelines

SDMMC, FMC, QUADSPI Interface Layout

Signal layout for SDMMC, FMC, and QUADSPI interfaces.

Embedded Trace Macrocell (ETM) Interface Layout

Signal layout guidelines for the ETM interface.

Conclusion and Application Note Usage

Document Revision History