Power supplies AN4938
14/48 DocID029918 Rev 1
Figure 6. PVD threshold
1.3.3 Analog voltage detector (AVD)
The AVD can be used to monitor V
DDA
power supply by comparing it to a threshold selected
through the ALS[1:0] bits of the PWR power control register (PWR_CR1). The threshold
value can be configured to 1.7, 2.1, 2.5 or 2.8
V (refer to the devices datasheets for the
actual values).
The AVD is enabled by setting the AVDEN bit in PWR_CR1 register. An interrupt can be
raised when V
DDA
goes above or below the configured threshold.
1.3.4 System reset
A system reset sets all the registers to their default values except the reset flags in the clock
controller RCC_RSR register and the registers in the backup domain (see
Figure 7).
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset).
2. Window watchdog end of count condition (WWDG reset).
3. Independent watchdog end of count condition (IWDG reset).
4. A software reset (Software reset).
5. A low-power management reset.
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