ST STM32H7 Series Application Note

Secure modes are orthogonal to the existing modes, Thread and Handler. Thus, there can be a Thread or
Handler mode in each secure mode (see the figure below).
Figure 3. Armv8-M TrustZone® execution modes
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Handler mode
Thread mode
Armv6-M/Armv7-M
Handler mode
Thread mode
Arm TrustZone system security
Armv8-M
Handler mode
Thread mode
Secure
Nonsecure
On typical firmware architecture running on Armv8 TrustZone®, the nonsecure domain executes the application
and the OS tasks, while the secure domain executes the secure application and the system root-of-trust
mechanisms.
4.3 Dual-core architecture
In dual-core products, one core can act as secure while the other is nonsecure. Some products,
such as dual‑core STM32WL devices in particular, feature a hardware support to propagate the secure attribute to
memory and peripherals, ensuring that robust runtime isolation implementation is possible.
A dedicated security controller is added to the dual-core STM32WL devices to facilitate the isolation.
Instead of using attribution units, the secure NV memory dedicated to securable CPU2 is defined in the flash
memory interface configuration. Key peripherals such as the DMA must convey the secure context (refer to the
user manual Getting started with STM32CubeWL for STM32WL series (UM2643) for details about this hybrid
architecture).
Figure 4. Simplified diagram of dual-core system architecture
DT67318V1
AHB
CPU1
nonsecure
MPU
CPU2
secure
MPU
DMA
Flash interface
SRAM
AHB/APB bridge
Bus masters Slaves
Security
controller
AN5156
Dual-core architecture
AN5156 - Rev 8
page 17/56

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English