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ST STM32H743I-EVAL - Hardware Layout and Configuration

ST STM32H743I-EVAL
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DocID030511 Rev 1 9/69
UM2198 Hardware layout and configuration
68
8 Hardware layout and configuration
The STM32H743I-EVAL Evaluation board is designed around the STM32H743XIH6
(240+25-pin TFBGA package) microcontroller. The hardware block diagram (see Figure 2)
illustrates the connection between STM32H743XIH6 and the peripherals (SDRAM, SRAM,
NOR Flash,
Twin Quad-SPI Flash, color LCD, USB OTG connectors, USART, Ethernet,
Audio, FD-CAN, microSD 3.0 card and embedded ST-LINK). Figure 3 helps users to locate
these features on the Evaluation board. The mechanical dimensions of the board are
showed in Figure 4.
Figure 2. Hardware block diagram
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