ST STM32L496 Series - User Manual

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October 2017 DocID029937 Rev 2 1/22

AN4943

Application note

Using the Chrom-ART Accelerator™ to refresh an LCD-TFT

display on STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers

Introduction

The purpose of this application note is to highlight how to refresh an LCD-TFT display via

the FSMC interface using the Chrom-ART Accelerator™ on

STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers.

The STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers implement a Chrom-Art

Accelerator™ (DMA2D) that is a specialized DMA dedicated to image manipulation.

It can perform the following operations:

• Filling a part or the whole of a destination image with a specific color

• Copying a part or the whole of a source image into a part or the whole of a destination

image with a pixel format conversion

• Blending a part and/or two complete source images with a different pixel format and

copying the result into a part or the whole of a destination image with a different color

format.

On the STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers, the flexible static memory

controller (FSMC) is used to access the LCD-TFT display through a parallel interface.

This application note explains on:

• How to connect the LCD-TFT display to the FSMC interface

• How to configure the DMA2D for the LCD-TFT display refresh

• How to use the DMA2D byte reordering features to directly drive Intel 8080 displays.

To fully benefit from this application note, the user should be familiar with the STM32

Chrom-ART Accelerator™ (DMA2D) as described in the STM32L4x6 advanced Arm

based 32-bit MCUs reference manual (RM0351) and the STM32L4Rxxx/L4Sxxx advanced

Arm

-based 32-bit MCUs reference manual (RM0432) available from the

STMicroelectronics website www.st.com.

Table 1. Applicable products

Type Product lines and part numbers

Microcontrollers

STM32L496AE, STM32L496AG, STM32L496QE, STM32L496QG,

STM32L496RE, STM32L496RG, STM32L496VE, STM32L496VG,

STM32L496ZE, STM32L496ZG

STM32L4A6AG, STM32L4A6QG, STM32L4A6RG, STM32L4A6VG,

STM32L4A6ZG

STM32L4R5/S5 line, STM32L4R7/S7 line, STM32L4R9/S9 line

www.st.com

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Summary

Chrom-ART Accelerator (DMA2 D) application use case overview

LCD-TFT display on FSMC

Hardware interface description

Details signals used for FSMC to LCD-TFT display connection.

Display Command Set (DCS) software interface

Describes control via FSMC bus using software commands.

Controlling the D;CX signal with STM32 L496 xx;L4 A6 xx;L4 Rxxx;L4 Sxxx microcontrollers

Explains D/CX signal for distinguishing commands from data transfers.

Chrom-ART Accelerator (DMA2 D) configuration in STM32 CubeL4

LCD partial refresh

Provides an example of DMA2D configuration for LCD partial refresh.

New DMA2 D features to support Intel 8080 displays

Intel 8080 interface color coding

Explains Intel 8080 color coding and its mismatch with STM32 memory.

DMA2 D reordering features

Covers DMA2D output FIFO reordering for display alignment.

DMA2 D reordering use case examples

Demonstrates DMA2D operations for byte order in display interfaces.

The document describes the use of the Chrom-ART Accelerator™ (DMA2D) on STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers to refresh LCD-TFT displays. This application note focuses on how to leverage the DMA2D for efficient image manipulation and display updates, reducing the load on the CPU and system DMA resources.

Function Description:

The core function of this application note is to explain how to use the Chrom-ART Accelerator™ (DMA2D) to manage LCD-TFT display refreshes via the Flexible Static Memory Controller (FSMC) interface. The DMA2D is a specialized DMA designed for image manipulation, capable of several key operations:

Filling: It can fill a portion or the entirety of a destination image with a specified color.
Copying: It can copy a part or the whole of a source image to a destination image, with optional pixel format conversion.
Blending: It can blend one or two complete source images, potentially with different pixel formats, and output the result to a destination image with a different color format.

In a typical display application, the process involves two main steps:

Frame Buffer Content Creation: The frame buffer is constructed by composing graphical primitives such as icons, pictures, and fonts. This task is usually handled by the CPU running a graphical library, but it can be significantly accelerated by the DMA2D. The more frequently the frame buffer is updated, the smoother the animations will appear.
Frame Buffer Display: The completed frame buffer is transferred to the LCD-TFT display through a dedicated hardware interface. This transfer can be managed by the CPU, the system DMA, or, as highlighted in this document, by the Chrom-ART Accelerator™ (DMA2D). Using the DMA2D for this step frees up the CPU and system DMA for other tasks.

The STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers utilize the FSMC as the hardware interface for the LCD-TFT display. Graphical primitives are typically stored in external Quad-SPI Flash memory, while the frame buffer resides in internal SRAM. The DMA2D can efficiently transfer this frame buffer from internal SRAM to the LCD-TFT display.

Important Technical Specifications:

Microcontrollers: STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx series. Specific part numbers include STM32L496AE, STM32L496AG, STM32L496QE, STM32L496QG, STM32L496RE, STM32L496RG, STM32L496VE, STM32L496VG, STM32L496ZE, STM32L496ZG, STM32L4A6AG, STM32L4A6QG, STM32L4A6RG, STM32L4A6VG, STM32L4A6ZG, and the STM32L4R5/S5, STM32L4R7/S7, and STM32L4R9/S9 lines.
Accelerator: Chrom-ART Accelerator™ (DMA2D).
Display Interface: Flexible Static Memory Controller (FSMC).
FSMC Signals:
- A[25:0]: Address bus (Output)
- D[15:0]: Bidirectional data bus (Input/Output)
- NE[x]: Chip select, x=1..4 (Output)
- NOE: Output enable (Output)
- NWE: Write enable (Output)
LCD-TFT Signals (Type B Display Bus Interface - DBI):
- D/CX: Data/command control signal (Input/Output)
- D[15:0]: Bidirectional information signals bus (Input/Output)
- CSX: Chip select control signal (Output)
- RDX: Read control signal (Output)
- WRX: Write control signal (Output)
- TE: Tearing effect (Output)
- RESX: Reset (Output)
Color Depths and Bus Widths Supported by DMA2D Reordering:
- 8bpp (256 colors): 8-bit (No Red/Blue swap, No Byte swap), 16-bit (No Red/Blue swap, Byte swap)
- 16bpp (64k colors): 8-bit (No Red/Blue swap, Byte swap), 16-bit (No Red/Blue swap, No Byte swap)
- 18bpp (262k colors): 8-bit (Red/Blue swap, No Byte swap), 16-bit (Red/Blue swap, Byte swap)
- 24bpp (16.7M colors): 8-bit (Red/Blue swap, No Byte swap), 16-bit (Red/Blue swap, Byte swap)
DMA2D Reordering Features:
- Red and Blue Swap: Swaps the red and blue color components. This feature is available on STM32L4 Series and STM32L4 Plus Series.
- Byte Swap: Swaps the MSB and LSB bytes of a half-word in the output FIFO. This feature is present only on the STM32L4 Plus Series.

Usage Features:

Full and Partial Refresh: The DMA2D can update either the entire display image (full refresh) or only a specific part of it (partial refresh), offering flexibility for dynamic content.
CPU/DMA Offloading: By using the DMA2D for frame buffer transfers, the CPU and system DMA are freed from these tasks, allowing them to handle other application logic, improving overall system performance.
Display Command Set (DCS) Interface: LCD-TFT displays are controlled via software commands conforming to the MIPI Alliance specification for DCS, transmitted over the FSMC bus. These commands configure the display module and transfer frame buffer data.
D/CX Signal Control: The D/CX signal, which distinguishes between command and data transfers, can be controlled in two ways:
1. Dedicated GPIO: A GPIO pin can be used to manually set the D/CX signal to '0' for commands or '1' for data.
2. FSMC Address Bit: A specific address bit of the FSMC address bus can be used to automatically control the D/CX signal. This method simplifies software by reserving a "low level" address for command transfers and a higher memory map range for data transfers. The DMA2D increments the address bus during data transfers, so a "high enough" FSMC address bit must be chosen to maintain its value throughout the frame buffer transfer.
Intel 8080 Display Support: The new DMA2D byte reordering features specifically address the mismatch between STM32's little-endian pixel data storage and Intel 8080 display's requirement for most significant byte first transmission. This allows direct driving of Intel 8080 displays from a frame buffer with classic RGB order without additional software manipulation.
Example Code: The application note refers to STM32Cube examples (e.g., STM32Cube_FW_L4\Firmware\Projects\STM32L496G-Discovery\Examples\DMA2D\DMA2D_MemToMemWithLCD) that demonstrate how to configure the DMA2D for LCD partial refresh.

Maintenance Features:

Hardware Fix for Byte Swap (for MCUs not supporting byte swap): For microcontrollers that do not support the byte swap feature, a hardware workaround is suggested: swapping the data lines of the LCD interface on the board. Specifically, display D[15:8] lines are connected to FSMC D[7:0] lines, and display D[7:0] lines are connected to FSMC D[15:8] lines. This provides a solution for achieving the correct byte order when the DMA2D's byte swap feature is unavailable.
Reference Manuals: The document emphasizes familiarity with the STM32L4x6 and STM32L4Rxxx/L4Sxxx advanced Arm®-based 32-bit MCUs reference manuals (RM0351 and RM0432, respectively) for a comprehensive understanding of the DMA2D.
HAL Library Functions: The configuration of the DMA2D is performed by programming specific registers through high-level HAL library functions, simplifying development.