ST STM32L496 Series

New DMA2D features to support Intel 8080 displays AN4943
18/22 DocID029937 Rev 2
5.3.2 24bpp/18bpp over 8-bit FSMC data bus interface
The red and blue swaps are required to get the correct order of bytes for 24bpp displays
using an 8-bit data bus.
Figure 9 shows the red and blue swap operation done by the DMA2D allowing to have the
good bytes order.
Figure 9. DMA2D operations to support 24bpp over 8-bit interface
MSv48351V1
8-bit FSMC data bus
B0 [7]
B0 [6]
B0 [5]
B0 [4]
B0 [3]
B0 [2]
B0 [1]
B0 [0]
G0 [7]
G0 [6]
G0 [5]
G0 [4]
G0 [3]
G0 [2]
G0 [1]
G0 [0]
R0 [7]
R0 [6]
R0 [5]
R0 [4]
R0 [3]
R0 [2]
R0 [1]
R0 [0]
1
2
3
4
Transfer
number
R1 [7]
R1 [6]
R1 [5]
R1 [4]
R1 [3]
R1 [2]
R1 [1]
R1 [0]
B0 [7]
B0 [6]
B0 [5]
B0 [4]
B0 [3]
B0 [2]
B0 [1]
B0 [0]
G0 [7]
G0 [6]
G0 [5]
G0 [4]
G0 [3]
G0 [2]
G0 [1]
G0 [0]
R0 [7]
R0 [6]
R0 [5]
R0 [4]
R0 [3]
R0 [2]
R0 [1]
R0 [0]
@+0
@+1
@+2
B1 [7]
B1 [6]
B1 [5]
B1 [4]
B1 [3]
B1 [2]
B1 [1]
B1 [0]
@+3
Memory
Pixel 0
Pixel 1
B0 [7]
B0 [6]
B0 [5]
B0 [4]
B0 [3]
B0 [2]
B0 [1]
B0 [0]
G0 [7]
G0 [6]
G0 [5]
G0 [4]
G0 [3]
G0 [2]
G0 [1]
G0 [0]
R0 [7]
R0 [6]
R0 [5]
R0 [4]
R0 [3]
R0 [2]
R0 [1]
R0 [0]
R1 [7]
R1 [6]
R1 [5]
R1 [4]
R1 [3]
R1 [2]
R1 [1]
R1 [0]
Red blue swap
@+0
@+1
@+2
@+3
D7
D6
D5
D4
D3
D2
D1
D0
Pixel 0 Pixel 1
Green component
Red component
Blue component