DocID029937 Rev 2 13/22
AN4943 New DMA2D features to support Intel 8080 displays
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5 New DMA2D features to support Intel 8080 displays
On the STM32 microcontrollers, the pixel data are stored in the frame buffer memory in little-
endian format. This means that the least significant byte is stored at the lowest address and
the most significant byte is stored at the highest address.
For example in case of the RGB888 pixel format, the blue component is stored at address 0
while the red component is stored at address 2.
When the pixel data are transmitted to the LCD display via the FSMC, it starts with the least
significant byte first, which is the blue component in this example.
This creates a mismatch with some Intel 8080 LCD display color coding which requires the
most significant byte to be transmitted first (red component in case of the RGB888 pixel
format).
This mismatch requires extra byte reordering steps to get the right byte order before
transmitting the pixel data through the FSMC.
The new DMA2D byte reordering features allow to reorder the data in the DMA2D output
FIFO, enabling to directly drive the LCD displays from a frame buffer with a classic RGB
order without any extra software manipulation.
5.1 Intel 8080 interface color coding
The Intel 8080 is a common interface standard for the LCD displays. It is a parallel bus
interface supporting 8, 9, 16 and 18-bit bus.
This section shows the Intel 8080 display color coding that creates a mismatch with a
classic RGB order in the STM32 memory.
• 24bpp (16.7M colors) and 18bpp (262k colors) over 16-bit interface
Figure 5 shows the color coding for transmitting 24bpp data over a 16-bit bus interface on
Intel 8080 displays.
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