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Supermicro SUPERSERVER 2028TP-HC0R - Page 100

Supermicro SUPERSERVER 2028TP-HC0R
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7-6
SUPERSERVER 2028TP-HC0R/HC0TR/HC0FR USER'S MANUAL
CPU Conguration
This submenu displays the following CPU information as detected by the BIOS. It

Processor Socket
Processor ID
Processor Frequency
Processor Max Ratio
Processor Min Ratio
Microcode Revision
L1 Cache RAM
L2 Cache RAM
L3 Cache RAM
CPU 1 Version
CPU 2 Version
Clock Spread Spectrum
Select Enabled to allow the BIOS to monitor and attempt to reduce the level of
Electromagnetic Interference caused by the components whenever needed. The
options are Disabled and Enabled.
Execute Disable Bit (Available if supported by the OS & the CPU)
Select Enable for Execute Disable Bit Technology support, which will allow the
processor to designate areas in the system memory where an application code can

codes to overwhelm the processor to damage the system during an attack. This
feature is used in conjunction with the items: "Clear MCA," "VMX," "Enable SMX,"
and "Lock Chipset" for Virtualization media support. The options are Enable and
Disable. (Refer to Intel and Microsoft websites for more information.)
PPIN Control
Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in
the system. The options are Unlock/Enable and Unlock/Disable.

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