Supermicro SuperWorkstation 7049GP-TRT - Page 16

16
SuperWorkstation 7049GP-TRT User's Manual
JPCIE8
PCIE 3.0 x16
Slot 8
32GB/s
32GB/s
x 16
x 4
Slot 6
JPCIE6
PCIE 3.0 x16
UL1
JPCIE9
PCIE 3.0 x16
Slot 9
JPCIE4
PCIE 3.0 x16
Slot 4
JPCIE2
PCIE 3.0 x16
port 1,2(USB3.0)
+
port 11,12(USB2.0)
M.2 CONN
PCIE 3.0 x4
HDR 2x5
x4
VR13
6+1 PHASE
205W
port 8,9(USB2.0)
port 3,4(USB3.0)
+
port 2,3(USB2.0)
TYPE A(USB3.0)
port 5(USB3.0)
+
port 10(USB2.0)
P2
x16
P0
DMIPE3 PE2 PE1
PE2 PE1 DMIPE3
DDR4 DIMM
REAR (USB2.0)
port 4,5(USB2.0)
DDR4 DIMM
#1
B
DDR4 DIMM
x16
x16
DMI
PET [4,5,6,7]
PHY
RTL8211E
USB2.0 [7] ESPI
PET9
#1
DDR4 DIMM DDR4 DIMMDDR4 DIMM
sSATA Gen3 [4..5]
BMC
REAR(USB3.0)
AST2500
DDR4 DIMM
A
DDR4 DIMM
D
E
#1
#1 #1
#1#1
#1
Slot 10
x16
PCIE 3.0 x16
JPCIE10
BMC SPI
SPI
PCH
SPI FLASH
32MB BMC
DDR4
VGA
IPMI LAN
RJ45
S-SATA4
SATA Gen3 [0..3]
S-SATA5
HDR 2x10
HWM
COM1
NC-SI(RMII)
USB3.0 [1..5]
USB2.0 [7..12]
x16
EXT CONN
JNCSI1
VCCP1&2
32GB/s
Slot 11
JPCIE11
PCIE 3.0 x4
DDR4 DIMM
#2
#1
DDR4 DIMM
#2
#1
F
#1
#2
DDR4 DIMM
C
#2
#1
DDR4 DIMM
To BMC RMII port
NC-SI
JLAN1
RJ45
JLAN2
RJ45
Slot 2
I-SATA-0~3
IPASS CONN
SATA Gen3 [4..7]
I-SATA-4~7
IPASS CONN
PET [0,1,2,3]
x4
X550
10G
10G
USB2.0 [2..5]
P2 P1
UPI UPI UPI
P0
P0
COM2
MUX
PCH SPI
SPI FLASH
64MB BIOS
TPM Header
HD LINK
ALC888 AUDIO FP
B
A
C
D
EF
(USB3.0) (USB2.0)
CPU 2
CPU 1
Figure 1-5. Intel® C621 Chipset: System Block Diagram
Note: This is a general block diagram and may not exactly represent the features on your
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motherboard.