Tait TB9100 - Page 116

116 Appendices TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
IPB5
LWP1
VF1
J4 I/O Input Port B[5]
Load/Store Watchpoint 1
Visible Instruction Queue Flush Status 1
IPB6
DSD1
AT0
K3 I/O Input Port B[6]
Development Serial Data Input
Address Type 0
IPB7
PTR
AT3
H1 I/O Input Port B[7]
Program Trace
Address Type 3
IRQ0
V14 I/P Interrupt Request 0
IRQ1 U14 I/P Interrupt Request 1
IRQ2
RSV
H3 I/P Interrupt Request 0
Reservation
IRQ3
CR
H2 I/P Interrupt Request 3
Cancel Reservation
IRQ4
KR
RETRY
SPKROUT
K1 I/O Interrupt Request 4
Kill Reservation
Retry
Speaker Out
IRQ7
MTXCLK
W15 I/O Interrupt Request 7
MII Transmit Clock
L1CLKRB
TOUT3
CLK6
PA2
R18 I/O Receive clock for the serial interface TDMb
Timer 3 output
Clock input for SCCs and SMCs or BRG clock
General-purpose I/O port A, bit 2
L1RSYNCA
PC4
T17 I/O Receive sync input for serial interface TDMa
General-purpose I/O port C, bit 4
L1RxDA
PA8
L17 I/O Receive data input for the serial interface TDMa
General-purpose I/O Port A, bit 8
L1RxDB
PA10
J17 I/O Receive data input for the serial interface TDMb
General-purpose I/O Port A, bit 10
L1ST1
RTSI1
PB19
N19 I/O Output strobe from the serial interface.
Request to send modem line for SCC1
General-purpose I/O Port B, bit 19
L1ST2
DREQ1
PC14
D18 I/O Output strobe from the serial interface
IDMA channel 2 request input
General-purpose I/O port C, bit 14
L1ST2
PB18
RXADDR4
n17 I/O Output strobes from the serial interface
General-purpose I/O Port B, bit 18
UTOPIA multi-PHY receive address line 4
L1ST3
L1RQb
PB17
PHREQ[1]
RXADDR1
P18 I/O Output strobe from the serial interface
D-channel request signal for serial interface TDMb
General-purpose I/O port B, bit 17
Least significant bit of PHY request bus
UTOPIA multi-PHY receive address line 1
Table 8.10 MPC859T Port Assignments (Continued)
Pin Name Pin No. Type Function