TB9100 Reciter Service Manual Network Circuitry 41
© Tait Electronics Limited January 2006
outputs are combined into a single unified bus, ie. a von Neumann
architecture, for external memory and peripheral accesses.
As well as address translation, the memory managers can apply protection
attributes to areas of memory. The parameters for translation and protection
are stored in tables in main memory. To speed up the translation process the
most recently used parameters are stored in internal registers called
Translation Lookaside Buffers; ITLB for the instruction memory manager
and DTLB for the data memory manager.
Debug Facilities and
Program Loading
The MPC provides comprehensive internal debug facilities to support the
software debugging process. A description of the full functionality of the
debug capabilities is outside the scope of this document; a thorough study
of chapter 45 of the MPC866 user’s manual (reference 2) is recommended.
The MPC debug interface can be activated directly out of reset, or upon the
occurrence of one of a number of machine exceptions. Activation of debug
mode out of reset requires the presence of an external debugger connected
to the debug connector, J100. Without the debugger connected, the MPC
operates normally and starts executing code from its program memory until
a machine exception occurs. These machine exceptions can be handled
internally by the interrupt service software or can be configured to start
debug mode.
Once debug mode is activated, the processor core fetches its instructions
from the debug interface rather than program memory. This allows the
processor registers and memory to be examined, or changed, and code to be
downloaded by the external debug tool. This download mode is also used
for transferring the bootloader software into the external flash EPROM on
a newly manufactured board.
If debug mode has been entered as a result of an exception, the cause of that
exception is indicated in the debug interface registers. The debug interface
also allows the setting up of breakpoints and watch-points. The watch-point
and breakpoint comparators can detect accesses to defined address(es) or
force a processor exception (interrupt) when a certain address is accessed,
even when the MPC is operating at full speed. Watch-point flags are
externally visible on test points TP202-TP203 and TP207-TP208 for
triggering logic analyzers or oscilloscopes.
The external connection to the debug interface is through a simple full-
duplex clocked serial interface. Data is clocked into the debug interface on
the Development Serial Data In (DSDI) pin; data is clocked out on the
Development Serial Data Out (DSDO) pin. Data is clocked in on the rising
edge of the Development Serial Clock (DSCK) and out on the falling edge
of DSCK. The state of DSCK during a processor reset determines whether
debug mode is started out of reset. These serial interface pins are brought
out to connector J100 along with the reset signals (HRESET
, SRESET) and
the CPU status pins (VFLS0, VFLS1).
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