TB9100 Reciter Service Manual Network Circuitry 85
© Tait Electronics Limited January 2006
5.9.7 Power-on Reset
A power-on-reset signal is required for initializing various chips on the
board; this is provided by CPU supervisor chip U901. On power up this
chip asserts its RST
output low and holds it low until the +3.3V supply
reaches its normal operating voltage. U901 also incorporates a further time
delay of 240ms (nominal) to allow other circuitry to stabilize before releasing
RST
.
Since U901 monitors only the +3.3V supply, use is made of the Power-
Good (PGOOD) status signal from U900 to ensure that the +1.8V supply
is also within specification before releasing RST. PGOOD is an open-drain
output that pulls low if either the +3.3V or +1.8V supplies deviate from
their nominal value by more than 7.5%. When PGOOD goes low it
reduces, through R911 and R907, the supply voltage seen by U901, thus
forcing a reset condition. Switch S900 also simulates a power supply voltage
drop to U901, allowing a manual reset operation.
Neither the +1.6V nor the +6V supplies are monitored by the power-on
reset circuit.
5.9.8 Board Status Signal
Since the ASIF and reciter digital board have separate power converters, it is
inevitable that one board powers up before the other. If the powered board
drives signal lines to the unpowered board, there is a potential for damage to
occur, through chip latch-up, when the second board powers up.
In order to coordinate the power-up sequence between the ASIF and the
reciter digital board a hardware handshaking line, ASIF_RDY, is provided.
This is controlled by the power-on reset circuit and the MPC to indicate the
ASIF’s readiness to run: when the ASIF is not ready to run it holds the
ASIF_RDY line low. By sensing the level on this line, the reciter board can
determine whether the ASIF is powered up and ready to run. However, the
current reciter hardware design does not support the ability to sense this line.
When the ASIF is not powered, the ASIF_RDY line is held low through
D903a. When the ASIF is powered-up, but still held in reset, the
ASIF_RDY line is held low through D903b. When the power-on reset is
released, ASIF_RDY remains held low by transistor Q910. Finally, when the
ASIF MPC has completed its initialization, it drives the ASIF_NRDY line
low, turning off Q910. The ASIF_RDY line is then pulled high by R922,
indicating that the ASIF is ready to run.
The ASIF_RDY handshaking line can also be used by the ASIF to
determine the status of the reciter digital board. As yet, no hardware has
been implemented on the reciter board to fully support the function of the
handshake line, so the ASIF is limited to sensing the status of the reciter’s
main supply voltage. A +3.3V supply line is available from the reciter on pin
7 of connector J101: if this supply is not present, the ASIF_RDY line is
pulled low through diode D100.
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