TB9100 Reciter Service Manual 9
© Tait Electronics Limited January 2006
Harvard architecture A type of computer architecture that utilizes
separate memory spaces for executable code
and data. cf. von Neumann architecture
HW Hardware
I
2
C Inter-Integrated Circuit, a serial
communications interface mainly intended for
interconnecting ICs contained within a single
PCB
IPN Internal Part Number, TEL's internal part
numbering system.
ITLB Instruction Translation Lookaside Buffer
IU Integer Unit
JTAG Joint Test Action Group, a test interface
specification for PCB assembly testing
Little Endian A memory ordering scheme where the least-
significant byte of a word occupies a higher
memory address than the most-significant byte
c.f. Big Endian
LRU Least Recently Used, a method of updating
cache memory contents
lsb Least significant bit
LSU Load/Store Unit
LVTTL Low Voltage TTL, logic specified for operation
at 3.3V supply and compatible with 5V TTL
family logic levels ie. VIH = 2.0V and
VIL=0.8V
MAC Media access controller, an ethernet controller
McBSP Multi-channel Buffered Serial Port
MII Media Independent Interface, an interface for
ethernet PHY devices
MIPs Million Instructions Per Second
MMU Memory Management Unit
MOSFET Metal Oxide Semiconductor Field Effect
Transistor
MPC MPC859TPZ133 PowerQUICC
microprocessor
NMI Non-maskable interrupt
OTP One Time Programmable, a non-volatile
memory device that cannot be erased and
reprogrammed after initial programming
msb Most significant bit
PBGA Plastic BGA
PCM Pulse Code Modulation
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