Theory of Operation—2465B/2467B Service
bits are clocked into register U150: one to produce the
CTC signal, one to control the scale illumination circuit
during SGL SEQ display mode, and two (CNTL1 and
CNTL2) to control the state of the measurement PAL,
U975.
The CTC control bit is used to enable a sweep-start
linearity circuit in the A Sweep circuitry (diagram 5) on the
2 ns and 20 ns per division sweeps.
Analog Control Demultiplexer
When enabled by the Address Decode circuitry, Analog
Control Demultiplexer U170 directs the analog levels
applied to pin 3 from DAC U2101 (diagram 2) to one of six
sample-and-hold circuits. In the Preamplifier circuitry, the
sample-and-hold circuits maintain the VAR gain and DC
Bal control-voltage levels applied to both the Channel 1
and Channel 2 Preamplifiers U100 and U200 between
updates. Two of the Demultiplexers outputs direct analog
levels to the Holdoff and Channel 2 Delay offset sample-
and-hold circuits (diagram 5). Routing is determined by the
three-bit address from register U2301 (diagram 2) applied
to Demultiplexer U170 on pins 9, 10, and 11.
Channel 1 Preamplifier
Channel 1 Preamplifier U100 converts the single-ended
input signal from the Channel 1 Attenuator to a differential
output signal used to drive the Vertical Channel Switch.
The device produces either amplification or attenuation in
predefined increments, depending on the control data writ-
ten to it from the Microprocessor. The preamp also has
provisions for VAR
gain,
vertical positioning, and a trigger
signal pickoff.
The Channel 1 vertical input signal is applied to pin A of
Channel 1 Preamplifier U100. Control data from the pro-
cessor is clocked into the internal control register via pin
22 (CD) by the clock signal applied to pin 23 ( CC ). The
data sets the device to have an input-to-output gain ratio
of 2, 4, or 10, depending on the VOLTS/DIV control set-
ting.
Two analog control voltages set by DACs modify the
differential output signal at pins 9 and 10. The front-panel
Channel 1 POSITION control supplies a position signal to
U100 pin 17 (via MUX U2530 and sample-and-hold U2430
and C2432) that vertically positions the Channel 1 display
on the CRT. A DC Bal signal is applied to pin 2 of U100
from MUX U170 via the sample-and-hold circuit composed
of U160A and C177. This DC BAL signal is a dc offset-null
level that is determined during the automatic DC Bal pro-
cedure. The offset value is stored as a calibration constant
in RAM and is recalled at regular intervals to set the DC
Bal level, holding the Preamplifier in a dc balanced condi-
tion.
The Channel 1 VOLTS/DIV VAR control is monitored by
the Microprocessor during the front-panel scanning
rou-
tine.
When the processor has determined where the
VOLTS/DIV VAR control is positioned, it causes DAC
U2101 (diagram 2) to produce a corresponding control
level and routes it to the VAR gain sample-and-hold circuit
composed of U160D, C179, and associated components.
The control voltage at the output of U160D (pin 14) sets
the variable gain of the Preamplifier.
A pickoff amplifier internal to U100 conditions the
trigger signal and provides the proper signal level at pin 15
to drive the A/B Trigger Generator (U500, diagram 5). The
pickoff point for the trigger signal is prior to the addition of
the vertical position offset, so the position of the signal on
the crt has no effect on the trigger operation. However,
the pickoff point is after the DC Bal and Variable gain
sig-
nals have been added to the signal so both of these func-
tions will affect trigger operation.
Common-mode signals are rejected from the trigger
sig-
nal by the circuitry composed of operation amplifier U450B
and associated components. The inverting input of U450B
(pin 6) is connected to the common-mode point between
APO+ (pin 12) and TPO- (pin 15) of U100. Any
common-mode signals present are inverted and applied to
a common-mode point between R451 and R453 to cancel
the signals from the differential output. A filter network
composed of LR 180 and the built-in circuit board capaci-
tor (5.6 pF) reduces trigger noise susceptibility. Trigger
sig-
nals for options are obtained from J100.
The Channel 1 input signal used to provide the horizon-
tal deflection for the X-Y displays is obtained from U100
pin 11. The components between pin 11 and the Horizon-
tal Output Amplifier provide phase compensation of the
signal.
During instrument calibration, the delay produced
by C115, C116, L115, R115, and variable capacitor C118
is matched to the 78-ns delay of the vertical delay line
(DL100, diagram 6).
Channel 2 Preamplifier
Operation of Channel 2 Preamplifier U200 is nearly
identical to that of the Channel 1 Preamplifier just
described.
The exceptions are that the output polarity of
the Channel 2 signal may be either normal or inverted and
that the signal obtained from the BPO+ output (pin 11) is
conditioned differently for a different purpose than in the
Channel 1 Preamplifier circuitry.
3a-15
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