Theory of Operation—2465B/2467B Service
Read-Write Latch U2440B _is used to delay the
processor's read/write signal (R/W) from the Microproces-
sor to meet hold-time requirements of the RAM. At the
same time, it generates delayed read and write enabling
signals of both polarities to meet the requirements of
Buffer U2350 and Latch U2450 (in the Microprocessor
Data Bus) and various other devices in the Readout cir-
cuitry (diagram 7).
When R/W goes LO for a write cycle and E goes HI,
Read-Write Latch U2440B is reset, and Q output (pin 9) is
held LO, Latch U2450 is in its transparent state at this
time,
and data from the Microprocessor is applied asyn-
chronously to the buffered Data Bus. At the end of the
write cycle, the R/W signal goes HI. The E signal also
goes through a negative transition, and data on the
Microprocessor data bus lines is latched into U2450. The
next positive transition of the
1.25-MHz
E signal (1/2 E
cycle after the R/W signal goes HI) clocks the HI level at
U2440B pin 12 (the D input) to the Q output, and the
~Q
output (pin 8) goes LO. The 1/2 E cycle delay between the
time R/W goes HI and the time that the Q output of
U2440B goes HI keeps Latch U2450 outputs on long
enough to meet the data hold time for the RAM. At the
end of that delay time, pin 1 of U2450 goes HI, and the
Latch outputs are switched to the high-impedance state to
isolate it from the buffered Data Bus.
READOUT FRAMING AND INTERRUPT TIMING. Binary
counter U2640 is used to generate a readout-framing
clock to the Readout circuitry and a real-time interrupt
request to the Microprocessor via inverter U2540C. The
readout-framing clock is a regular square-wave signal
obtained from U2640 pin 12 by dividing the
1.25-MHz
E
signal by 512 (2
9
). This clock tells the readout circuitry to
load the next block (subframe) of readout information to be
displayed.
(See "Readout" description for further
information concerning alphanumeric display.) The
real-
time interrupt request, which occurs every 3.3 ms, is
obtained from pin 2 by dividing the E signal by 8192 (2
13
).
When the real-time request occurs, IRQ (pin 4 of
U2140) goes LO, and the processor breaks from execution
of its mainline program. The Microprocessor first resets
Binary Counter U2640 by setting pin 19 of U2301 (diagram
2) HI (to generate the reset), then it resets pin 19 LO to
allow the counter to start again. At this time, the Micropro-
cessor sets analog control voltages and reads trigger
status from the Display Sequencer (diagram 5). When this
is completed, it reverts back to the mainline program.
In addition to the analog control and trigger status
update that occurs with each interrupt, on every fifth inter-
rupt cycle, the Microprocessor also scans the front-panel
potentiometers. Every tenth interrupt cycle, scanning the
front-panel switches and checking the 5042 DC inputs for
overloads is added to the previously mentioned tasks. If all
the tasks are not completed at the end of one interrupt
cycle,
the real-time interrupt request restarts the analog
updates, but as soon as those are accomplished, the
Microprocessor will pick up with its additional tasks where
it was before the interrupt occurred. This continues until all
tasks are completed. If any pot or switch changes are
detected,
the Microprocessor updates the analog control
voltages and the control register data to reflect those
changes prior to reverting back to the mainline program
instructions.
FRONT-PANEL SCANNING and
ANALOG CONTROLS
The Analog Control circuitry (diagram 2), under
Microprocessor control, reads the front-panel controls and
sets various analog control voltages to reflect these front-
panel settings. The calibration constants determined during
instrument calibration and the last "stable" front-panel
setup conditions are stored in battery backed up RAM. At
power-on the stored front panel information is used to
return the instrument to its previous state.
Hardware I/O
Data transfer from the Analog Control circuitry to the
Microprocessor is via Status Buffer U2220. Data bits
applied to the input pins are buffered onto the Data Bus
when enabled by the Address Decode circuitry. Via the
Status Buffer, the processor is able to (1) determine the
settings of front- and rear-panel pots and switches, (2)
determine instrument type (2465B or 2467B), (3) determine
if a triggered sweep is in progress, and (4) read the
con-
tents of the Readout RAM. When disabled, the buffer out-
puts are switched to high impedance states to isolate
them from the buffered Data Bus.
Data transfer from the Microprocessor to the Analog
Control circuitry is via registers U2210 and U2310. Via
register U2210, the Microprocessor is able to select the
3a-9
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