Theory of Operation—2465B/2467B Service
Of the addresses in the bottom 32K-byte memory
space,
only the lowest 8K-byt.es are further decoded.
Addresses in the lowest 2K-byte block of addresses will
cause U2250 to generate an enable signal to the RAM,
U2460.
Addresses in the next 2K-byte block of addresses
will enable U2550 to do the next state of address decod-
ing.
The next 4K-byte block of addresses will enable the
Buffer Board ROM section of U2160.
The level of decoding performed by U2550 uses
address bits BA4, BA5, and BA6 to separate the
addresses within the 2K-byte block of addresses 0800 thru
OFFF into 128 groups of 16 addresses. Address bits BA7
thru BA10 are not used in the decoding scheme, so each
of these 128 blocks is not uniquely identified. This results
in sixteen duplicate sections within the address block,
each consisting of eight groups of 16 addresses. The
upper fifteen sections in the address space are never
used;
therefore, decoding by U2550 may be more simply
thought of as eight groups of 16 address locations.
Addresses within these eight groups generate control
sig-
nals to other portions of the instrument.
The final level of address decoding is done by a pair of
three-to-eight-line decoders, U2650 and U2660. When
enabled by the Y7 output of U2550, these decoders
separate the highest 16-address group decoded by U2550
into 16 individual control signals.
Each of the control signals generated by the Address
Decode circuitry are present only as long as the specific
address defining that signal is present on the Address
Bus.
However, four of the addressable control signals
decoded by U2550 are used to either set or reset flip-flops
U2560A and B, and U2570A. The control signals are, in
effect, latched and remain present to enable multiplexers
U2521,
U2530, (diagram 2), and U170 (diagram 4). When
enabled,
these multiplexers route analog control signals
from the DAC (digital-to-analog converter) U2101 (diagram
2) to the various analog control circuits.
Read-only Memory (ROM)
The Read-only Memory consists of one 128K-byte
ROM and one 64K-byte ROM that contain operating
instructions (firmware) used to control processor (and thus
oscilloscope) operation. Addresses from the Microproces-
sor that fall within the top 24K-bytes of addressable space
cause one of the two read-only memory integrated circuits
to be enabled. (See Address Decode description.) Instruc-
tions are read out of the enabled ROM (or PROM) IC from
the address location present on its address input pins. The
eight-bit data byte from the addressed locations is placed
onto the Buffered Data bus (BDO through BD7) to be read
by the Microprocessor.
Random-Access Memory (RAM)
The RAM consists of integrated circuit U2460 and pro-
vides the Microprocessor with 8K-bytes of battery backed
up temporary storage space for data that is developed
during the execution of a routine. The RAM is enabled
whenever an address in the lowest 2K-byte of addresses
is placed on the Address Bus or whenever an address of
8000 thru 9FFF is placed on the Address bus. When writ-
ing into the RAM, the write-enable signal (WE) on pin 27 of
U2460 is set LO along with the chip enable (CE) signal on
pin 20. At the same time, the output-enable (OE) on pin 22
is HI to disable the RAM output drivers. Data is then writ-
ten to the location addressed by the Microprocessor. If
data is to be read from the RAM, the WE signal is set HI
to place the RAM in the read mode, and the OE signal is
set LO to enable the output drivers. This places the data
from the addressed location on the buffered Data Bus
where it can be read by the Microprocessor.
The RAM also provides non-volatile storage for the
calibration constants and the power-down front-panel set-
tings.
When power is applied to the instrument, the
Microprocessor reads the calibration constants and
gen-
erates control voltages to set up the analog circuitry. The
front-panel settings that were present at power-off are
recalled and the instrument is set to the operating mode
previous power off.
Timing Logic
The Timing Logic circuit composed of U2440B, and
U2540D generates time- and mode-dependent signals from
control signals output from the Microprocessor. The
enable (E) signal output from the Microprocessor is a 1.25
MHz square wave used to synchronize oscilloscope func-
tions to processor timing.
Data applied to the Address Bus, Data Bus, and
vari-
ous control signals are allowed to settle (become valid)
before any of the addressed devices are enabled. This is
accomplished by switching the E signal HI a short time
after each processor cycle begins. Inverter U2540D inverts
the polarity of the delayed enable signal and enables the
Address Decode stage only after the address bus has set-
tled.
3a-8
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