Tektronix 7704A User Manual

Circuit Description-7704A
Service
ιιιιιιιιωι
NOMMUMMEEM
MMMMMUMMMM
ιι r ιιι M ιιιι rr ι
MMOMMMEMME
MM =
MEMEMEWN - 0
F ig . 2-34 . Typ ical r ea d ou t d is p lay w h e r e only c h an n el 1 of
t h e
R ig h t V ertical a nd Β H o r izo n tal un its is d is p laye d .
lines . T h is row and column corres po nd to t he row and
column of t he C h aracter Selection M atrix i n
F
ig . 2-33 .
T
h e
stan d ard format for en codi ng i n formation onto t h e o
u
tput
lines is given in Table 2-2 . (Special p ur p ose pl u g-in
u n
its
may have t h eir own format for rea d out ; t
h ese special
formats will be d efine d in t
h e
ma
n uals for t h ese un its .)
TA BLE 2-2
Sta nd a r d R ea
d o ut F ormat
T h
e enco d
e d colu m n an d row data from t he p lug-i n
un
its is
selecte d b y t h e Column Data Switc h an d R ow Data
2- 4 2
Switch stages respectively .
T h
ese stages ta k
e
t
he
a
n
alog
currents from t
h
e
eig h
t data
lines (two c h a n nels from eac h
of t he fo
u r plug-in compartments) an d pro d uce α time-
m u lti p lexe
d
analog voltage out p ut containing all of the
colum n
or
row i nformation from t he p l u g-ins . T he Colu mn
Data Switch and
R
ow Data
Switc h
are
sequ enced by t h e
b inary C h annel
A
d d ress Co
d e from t h e Ch an nel Counter .
T h
e outpu t of
t h e d ata switc h es can b e discon n ecte d b y an
i npu t from t he M ain Inte r connect w h ile t he M ain Inter-
conn ect p rovi d es t he colum n an d r ow d ata to t h e remainder
of t h e R ea do u t System .
T he time-m
u lti p lexe d outp u t of t h e Colu m n Data
Switch is
monitore d by t h e Dis p lay-S k ip Generator to
d
etermine if it r eprese n ts vali d i nformation t h at s h oul d be
d is p
laye
d . Wh enever i nformation is not enco d ed in α
time-slot, t h e Display-S k ip Generator pr od uces - an out p ut
level to prevent t h e
Timer
stage
f r om p r oducing t h e co n trol
sig n als t
h
at
normally interru p tthe C RT d is p lay and present
α
c h aracter .
T he analog outputs of t h e Col u m n Data Switc h and R ow
Data Switch are con n ecte d to t h e Colu mn Deco d er an d
R ow Deco d e r stages respectively . T h ese stages sense t h
e
mag
n itu d e
of
t he analog voltage i np ut and pr odu ce an
o utp ut c urrent on one of ten lines . T h e out p uts of t
h
e
Col u mn Deco d er stage
are i dentified as C-1 t h roug h C-10
(col u mn 1 th roug h 10) correspo nd ing to t h e encode d
column informatio n . L i k ewise, th
e
out p uts of t
h
e
R
ow
Decoder stage are i d entifie d as
R
-1 t
h roug h R -10 (row 1
t h roug h 10) correspon d
ing
to t
he enco d ed row informa-
tion . T h e p rimary functio
n
of
the row an d colum n ou t p uts
is to select α c
h
aracte
r from t he C h aracter Selection M atrix
to be p ro du
ce d by t h e C h aracter Generator stage .
T
h
ese
ou t p uts are also
use d at oth er points wit h in t he system to
i nd icate
w hen certain info r mation h as
been en
co
de d . O ne
suc h stage is t he Zeros L ogic and
M emory . Duri ng ti m e-slot
1 (TS-1), t h is stage ch ec k s
if
zero-a
dd ing or p refix-s h ifting
information h as been enco d ed b y t
he plug-in un it, and
stores
it in memory until time-slots 5, 6, or
8
.
After storing
t h is
infor m ation, it triggers t h e Dis p la y -S k
i p Ge n erato r
stage so
t h at t h ere is no d isplay du
ring
ti
m e-slot 1 (as
define d by Stan d ard R eadout
F
ormat ;
see Table 2-2)
. Wh
en
time-slots 5, 6, and 8 occ
u r, t h e memory is addresse d and
any info r mation stored
t h ere duri ng time-slot 1 is tra
n
s-
ferred to th e input of t he
Colu mn Deco d er stage to mo d
ify
t he analog
d ata du ring t he applica b
le time-slot .
Also,
t h e Zeros L ogic an d
M emory stage p ro du ces t
h
e
ID EN TI F Y fu nction .
Wh en ti m e-slot 1 is enco d e d for
ID EN TI F Y (col u mn 10, row
3), t h is stage produ ces an
o
u t
p
ut level, w h ic h
connects t he Colum n Data Switc
h
an
d
R ow Data Switch to α co
d i ng netwo rk wit h in t
h e R eadout
System . T h en , d u r ing
time-slots 2 t h ro ug h 9, an
analog
cu r rent outpu t is pro
duced from t he Column
Data Switc h
an d R ow Data
Switch w h ic h a dd resses t
he correct points in
t he C h
aracter Selection M atrix
to d isplay t he wor d
"ID EN TI F Y" on the C
RT . T h e Zeros L ogic a nd
M emo r y
stage is reset after eac
h word b y the W o r d
Trigger p ulse .
Time-Slot Nu mbe r Descri
p tion
TS-1 Determines d ecimal
magnitu de
(nu m b e r of ze r os d
is p
laye
d or pre-
fix c
h
an ge
information) or t h e
ID EN TI F Y fu n ction (no display
d
u ri n g
t
h is time-slot) .
TS-2 In d icates
normal
or
inverted i nput
(no d isplay for normal) .
TS-3 In d icates cali b rated or
un cali b rate d
cond ition of
plug-in variable
control
(no
d isplay for cali b rate d
con d itio n ) .
TS-4 Scaling .
TS-5
N
ot
en
coded b y p
lug-in u nit . L eft
TS-6 b la nk to allow a dd ition of zeros by
TS-7 R ea d out System .
TS-8 Defines t he p refix w h ic h mo d ifies
the un its of measurement .
TS-9 Define t
h
e un its of meas
u reme n t
of
TS-10
t
he p lug-in unit . May be sta nda rd
u nits of measurement (V, Α , S,
etc .) or special u nits selected from
t h e C h aracter Selectio n M atrix .

Tektronix 7704A Specifications

General

Brand	Tektronix
Model	7704A
Category	Test Equipment
Language	English