Tektronix 7704A User Manual

Nu mber

P
age Num ber

P age
F ro n tis p iece

2-22

I npu t/out put ta b le fo r Α an d Β Trigger Selector 2-27
stages .
1-1

L i n e Selector assemb ly on rear pan el (s h own wit h 1-1
cover an d f u ses remove d ) .

2-23

Detaile d

b loc k

d iagram

of

Vertical

Inte r face

2-28
circu it
.
1-2 Α

7704 Α fro n t- p anel controls a ndco nn ectors .

1-2
1-2 Β

7704 Α rear- p anelcontrols a nd co nn ectors .

1-3
LIST OF ILLUSTRATIONS
7704 Α Service
2-24

I npu t/output ta b le for V ertical
Plug-in
Selector .

2-29
2-25

I npu t/o ut pu t tab le for V ertical Trace Sep aration 2-30
2-1

7704 Α b
loc
k
diagram
.

2-2

stage .
2-2

Cali b rator circuitdetaile d bloc k d iagram .

2-7

2-26

H orizo n tal I n terface circuit d etailed b loc k diag r am .

2-30
2-3

B loc k d iagram of L ogicCirc u it .

2-8

2-27

I np
ut/o u tp ut table
for H
orizo n tal Plug-in Selector
.

2-31
2-4

B rea k d ow n of
se
p
arate stages wit h in H orizo n tal

2-9

2-28

O
ut pu t Signals d etaile d b loc k d iagram .

2-32
L ogic
IC ( U
2573)
sh owing in pu ts a nd out p uts for
eac h stage .

2-29

Detaile d bloc k

d iagram

of

Inverter/ R ectifiers 2-34
circ u it .
2-5

(
Α
)
L ogic d iagram for Α Swee pLock
o
ut
stage
;
(
Β
) 2-10
Ta b le of i npu t/o u t pu t co mb i n atio n
s .

2-30

Si
m plifie d
schematic
of I n verter, R eg u lato r , and 2-35
Inverter Co ntrol
stages
.
2-6

( Α
)
L ogic diagr a m for Β Swee pLocko u t stage ;
(
Β
)
2-11
Ta b le of i n pu t/o u t pu t com b inatio n s .

2-31

Detaile d b loc k d iagram of L ow- V oltage R egu lators 2-38
circ
u it .
2-7

( Α ) L ogic d iagra m for Alter n ate Pulse Ge n erator 2-12
stage ;
(
Β ) Tableof i npu t/o u t pu t combinations .

2-32

L ocatio n of rea dou t wor d s on t h e CRT ide n tifying 2-40
t he origi n ati ng plu g-i n a nd c h a nn el (o ne com p lete
2-8

I npu t a ndo ut pu t p insfor Ζ -Axis L ogic IC .

2-13

frame
shown,
simulate d rea do u
t) .
2-9

(
Α ) L ogic d iagram for Ζ -Axis L ogic stage ;
(
Β
)
2-14

2-33

C h aracter Selection M atrix for 7704 Α R eadout 2-41
Tab le of i npu t/o u tp u t com b inations .

Syste m .
2-10

( Α ) L ogic d iagra m for H orizo n tal B i n ary stage ;
(
Β
)
2-16

2-34

Ty p ical r ea dou t d is p lay w h ere only c h a nn el 1 of 2-42
Table of i npu t/o utpu t co mb i n atio n s .

t h e

R ig h t V ertical a nd Β H o r izo n tal un its is
2-11

Input a n d o u tp ut pi n s for V ertical B i n ary IC .

2-17
2-35
2-12

(
Α
)
L ogic diagram for V ertical B i n ary stage ;
(
Β
)
2-18
Tab le of i npu t/o u tp ut combi n atio ns .

2-36
2-13

I np ut a nd o u t pu t pins for Plug-in B i n ary IC .

2-19

2-37

Detail of ou t pu t at pins 12, 13,
14,
a
nd
16
of

2-45
U 3433 .
2-14

( Α ) Logic d iagra m for Plug-in B i n ary stage ; ( Β ) 2-20
Table of in p u t/o u t pu t com b i n ations .

2-38

Time r stage op eration w he n Dis p lay-S k i pcond itio n 2-46
occ urs .
2-15

( Α ) Diagra m of Clock Ge n erato r stage ; ( Β ) Ide- 2-21
alize dwavefor
m s
for
Cloc k Ge n erator stage .
2-39 Time relations hip of
t
he time-slot (TS) p u lses 2-47
p r o du ce d by U 3445 .
2-16

(
Α
)
L ogic d iagram for V ertical Ch o pp ed B la nk i ng 2-22
stage ;
(
Β
)
Tab le of i npu t/output co mb i n atio ns .
2-40

Typical encod ing sc h eme for voltage-se n si ng pl u g- 2-49
2-17

I d ealize d waveforms for Vertical C h o pp ed B lan k - 2-23

i n u n it . Co d ing s h ow n for deflection factorof 100
i n g stage .

microvolts .
2-18 ( Α ) L ogic d iagra m for C hop Co u nter stage ; ( Β ) 2-24
Tab le of i nput/out p ut combi n ations .
2-19

L ogic diagra m of V ertical M od e L ogic stage .

2-25
2-20

Sim p lifie d schematic of trigger selectio n circ u itry . 2-26
2-41

I d
ealize
d c u
rre n
t
waveforms of :
(
Α ) R ow analog 2-50
d ata,
(
Β
)
Col u m n a n alog d ata .
2-42 Bloc k r e p r esentation of memo
r y
se qu
ence in 2-52
U 3401
.
2-21

I npu t levels at pin 4 of U 2404 an d U 2424 (so u rce 2-27

2-43

Typical o u tp u t waveforms for Zeros L ogic an d 2-54
of trigge r
ing signal is sh ow n in parent h eses) .

M emory stage op eratio n (at pi n7 of U 3401) .
d is p laye d .
Detaile db loc k d iagram of R ea d o u t Syste m . 2-43
O u tp u t waveforms ofTi m er stage . 2-45

Tektronix 7704A Specifications

General

Brand	Tektronix
Model	7704A
Category	Test Equipment
Language	English