Tektronix 7704A User Manual

Circuit Description -7704A
Service
its collector . T h is J um p Comman d is
connecte d to t h e
W ord Trigger stage to a d
vance t h e Ch annel Counter to t h e
next wor d an d to
reset t he Time-Slot Counter to time-slot
1 .
Zeros L ogic an d M
emory
T h e Zeros Logic and
M emory stage U 3401 stores d ata
enco d e d by t h e
P lug-in units to p rovi d e zeros-adding and
p refix-s h ifting
logic for t h e R eadou t System . T h e Strobe
pulse
at
pin 15 goes p ositive w h en t h e d ata h as stabilize d
an
d can be ins pected . T h is activates t h e Zeros L ogic and
M emory stage so t h at it can store t he enco d e d d ata .
Α
b loc k
re p resentation of t h e memory se q uence is s h own in
F
ig . 2-42 .
Typ ical output waveforms for t h e five p ossible input
con
d
itions t h at can occur are s h own in F ig . 2-43 . Wh en
time-slot 1 occurs, α store command is given to all of t h e
memories . If t h e plug-in unit encoded d ata for column 1, 2,
3, 4, or 10 during time-slot 1, t
h
e ap p ropriate memory (or
memories) is set .
N
otice t
h
at row
3 information from
t
h e
R
ow
Deco
d
er
must also be
present
at p in 16
for
d
ata
to be
stored
in
t
he memory
of
U 3401 .
2- 5 2
F ig . 2-42
. B
loc
k re p resentation of memory se qu e n ce in U 3401 .
If data was encoded d uring
time-slot 1, α negative-going
output is pro d uced at
pin 7 w h ile t he memories are being
set .
T h
is
negative-going p ulse is connecte d to t he base of
Q3414
in t
he Display-S k ip Generator to pro duce α Display-
Sk ip output .
Since t h e information enco d ed
during time-
slot
1 was only p rovi ded to set t
he memories and not
inten d ed to be displayed on t
he CRT at t h is time, t h e
Display-S k i p output prevents α rea
d out display during t h is
time-slot .
During time-slot 5, memory
Α
is interrogated .
If
information was store d in t h is memory, α p ositive-going
output is
produce d
at
pin 7 . T h is pulse is connecte d to p in
10 of t
h
e
Column Deco d er t h roug h Q3419 to a dd one unit
of
current
at
t h e in p ut of t he Column Deco d er .
T
h is
pro duces α zero after t he c h aracter d is played during
time-slot 4 . During time-slot 6, memory
Β
is interrogated to
see if anot h er zero s h oul d b e a dd e d . If anot h er
zero is
necessary, α secon d positive out p ut is produced at p
in 7,
w h ic h again results in α column 1 out put from t
h
e
Column
Deco d er an d α second zero in t h e C R
T
dis p lay .
Col u m
n 1
Colum n 2
Col u m n 3
Colum n 4
12
13
10
4
Colum n 10

14
Time-Slot 1

5
\

Store Comma nd
Ti
to all memories
R ow 3

16

io

En able to all memories
W or d
Trigger

9
R eset to all memo r ies
Interrogatio n pulses
Ti
m e-Slot 6

Ti m e-Slot 8
3

6
M emory
D
(I
d e n tify)

Tektronix 7704A Specifications

General

Brand	Tektronix
Model	7704A
Category	Test Equipment
Language	English