Tektronix 7834 User Manual

Theory of
Operation-7834
STORAGE LOCKOUT
FROM
18
(A)
U4428B

4O
DELAY GATE
FROM

.-
A TIME-BASE
UNIT
ALT MODE (HORIZ)
X-COMPENSATION
INHIBIT
(A
HORIZONTAL)
X-COMPENSATION
INHIBIT
(B
HORIZONTAL)
DELAY
MODE
CONTROL OUT
MAIN FRAME CHANNEL
SWITCH SIGNAL (DISPLAY
B)
Figure
3-6 . (A)
Logic diagram for B Sweep Lockout stage
;
(B)
Table of input/output combinations
.
Chopped Blanking, and
readout blanking signals are applied
to this stage to block
the output current and blank the crt
display
for vertical chopping, horizontal chopping, or
dur-
ing a
readout display .
Figure 3-8 identifies the inputs to
the Z-Axis Logic stage .
This circuit is current-driven
at all inputs except pins 5 and
15 . The current at
pins
1, 2, and 16 is variable from zero to
four milliamperes and is
determined by the applicable
current source to control
the output current at pin 8 .
The Vertical
Chopped Blanking signal connected to
pin 7,
and the
Horizontal Chopped Blanking connected to both
pins 6 and
7 through 04336, CR4487, CR4488, enable or
disable
this stage to control all output current .
Quiescently,
the
level
at
pins 6 and 7 is H I so that the intensity
current
from
pins 1, 2, 9, and 16 can pass to the output .
However,
pin 7 goes LO during Vertical Chopped
Blanking and both
pins 6 and 7 go LO for Horizontal Chopped
Blanking or
during a readout display . This blocks the output
current
and
the crt is blanked . The Vertical Chopped
Blanking
signal is connected to pin 7 of U4494
directly from pin 4 of
U4320 . The Horizontal Chopped
Blanking signal is connect-
ed to U4494 from pin
4
of
U4340 through LR4338, 04336
and CR4487, CR4488 . Notice that this
signal
is connected
3- 1 4
Q182,U92A
04468
SWEEPLOCKOUT
00

TO B TIME-BASE
0
UNIT
SEE MAIN INTERFACE
(1195-6) 1988-31
to the collector of
04336 . This transistor is normally
operating in the
saturated condition, and the H I
Horizontal
Chopped Blanking
level from U4340 is the collector
source
voltage . When the
Horizontal Chopped Blanking
level goes
LO, the
current through 04336 drops to
produce a corres-
ponding LO level at its emitter . This
level is connected to
pins 6 and 7 of U4494 through
CR4488 and CR4487
respectively .
Transistor 04336
also controls the levels at pins 6
and 7 for
readout displays
. The Z-Axis Logic Off
Command from the
Readout System
is connected to the base of 04336
through
V R4334 and R4335
. This level is normally HI, so 04336
operates as controlled by the
Horizontal Chopped Blanking
level at its collector
. When a readout display is to be pre-
sented, the Z-Axis
Logic Off Command drops LO
and this
level is coupled to
the
base of 04336 through
VR4334 .
Transistor 04336
is reverse biased to produce a LO
level
at
its emitter . This
level is coupled to pins 6 and 7 of
U4494
through CR4487
and CR4488 to block the Z-Axis
Logic
output current
during the readout display . (The
intensity of
the readout display
is determined by a separate
READOUT
intensity level connected directly to the Z-Axis
Amplifier ;
see CRT Circuit description .) Diode CR4486
clamps the
emitter of 04336 at about -0 .6 volt when the
transistor
is
off .

Tektronix 7834 Specifications

General

Brand	Tektronix
Model	7834
Category	Test Equipment
Language	English