7834
Instruction
FIGURE
NO
.
Frontis-
piece

7834
Features
.
.
. . . . . . . . . . . . . . . .
.1-1

7834
dimensional
drawing
. . . . .

. .
2-1

Front-panel
controls,
connectors
and
indicators
2-2

Rear-panel
controls
and
connectors
. .

. . . .
2-3

Definition of
graticule
measurement
lines
. . .
2-4

Location
of
readout
on
the
crt
identifying
the
originating
plug-in
and
channel
.

.
2-5

Location
of
readout
on
the
crt
when
REDUCESCAN
is
selected
. .

.

. . . . . . .
3-1

Basic
block
diagram
of
the
7834
Storage
Oscilloscope
. .

. . . .

. . . .
3-2

Detailed
block
diagram
of
the
Calibrator
and
Mode
Switch
. .

. . .

.

. .
3-3

Detailed
block
diagram
of
the
Logic
circuit
. .
3-4

Breakdown
of separate
stages
within
HorizontaLogic
IC
(U4428)
;
showing
inputs
and
outputs
each
stage
.

. .
.

. .

.

. .
3-5

(A)
Logic
diagram
for
A
Sweep
Lockout
Stage
;
(B)
Table
of
input/output
combinations
. . . .
3-6

(A)
Logic
diagram
for
B
Sweep
Lockout
stage
;
(B)
Table
of
input/output
combinations
. . . .
3-7

(A)
Logic
diagram
for
Alternate
Pulse
Generatostage
;
(B)
Table
of
input/output
combinations
3-8

Input
and
output
pins for
Z-Axis
Logic
IC
(U443-9

(A)
Logic
diagram
for
Z-Axis
Logic
stage
;
(B)
Table
of
input/output
combinations
. .
3-10

Input
and
output
pins for horizontal
binary
IC
(U4358)
. . . . . . . . . . . . . . . . . . . . . .
3-11 (A)
Logic
diagram
for
Horizontal
Binary
stage
;
(B)
Table
of
input/output
combinations
. . . .
3-12

Input
and
output
pins for
Vertical
Binary
IC
(U4368)
. . .

. . . . . . .
3-13

(A)
Logic
diagram
for
Vertical
Binary
stage
;
(B)
Table
of
input/output
combinations
. . . .
3-14

Input
and
output
pins for Plug-In
Binary
IC
(U4412)
. . .
.

. . . . . . . .
3-15

(A)
Logic
diagram
for Plug-In
Binary
stage
;
(B)
Table
of
input/output
combinations
. .
3-16

(A)
Diagram
of
clock
generator
stage
;

(B)
Idwaveforms
for
clock
generator
stage
.
3-17

(A)
Logic
diagram
for
Vertical
Chopped
Blankistage
;
(B)
Table
of
input/output
combinations
3-18

Idealized
waveforms
for
Vertical
Chopped
Blanking
stage
. . . . .

.

. .
3-19

(A)
Input
and
output
pins for
Chop
Counter
ICU4340
;
(B) Idealized
waveforms
for
Chop
Counstage.

. . .

. . . . . . . .
.
. . .
3-20

Logic
diagram
of
Chop
Counter
stage
. . . . .
3-21

Logic
diagram
of
Vertical
Mode
Logic
stage
. .
3-22

(A)
Logic
diagram
of
Trace
Separation
stage
;
(B)
Table
of
input/output
combinations
. .

.
3-23

Detailed
block
diagram
of
the
A
Trigger
Selectocircuit.

. . .

. .
3-24

Detailed
block
diagram
of
the
B
Trigger
Selectocircuit
.

. . . .

.
3-25

Detailed
block
diagram
of
the
Vertical
Interfaccircuit
.

. . .

. .
.
3-26

Location
of
readout
display
on
the
crt
identifyithe
originating
plug-in
and
channel
. .

. .
3-27

Character
selection
matrix
for
7834
Readout
System
. .

. .
3-28

Typical readout
display
where
only
Channel
2
of
the
Right
Vertical
and
B
Horizontal
units
is
displayed
. .

. . . .

.

. . .
3-29
Detailed
block
diagram
of
the
Readout
System
3-30
Output waveforms
of
the
Timer
stage
. . . . .
D
l
,
e
LIST
OF
ILLUSTRATIONS
PAGE
FIGURE
NO
.
PAGE
3-31
Detail
of
output
at
pins 12, 13,
14
and
16
of
. . . . .
viii
U2126
.
.
. .
. . . . . . . . . . . . . . . . . . . . . . .
3-40
. . . .
1-14
3-32
Timer
stage
operation
when
display-skip
condition
. . .
.2-2
occurs
. . . . . . . . . . . . . . . . . . . . . .
.3-41
. . . .
.2-4
3-33
Timer
relationship
of
the
time-slot
(TS)
pulses
. . . .
2-11
produced
by
Q3445
. .
.
. . . . . .
3-42
3-34
Typical
encoding
scheme
for voltage-sensing
plug-in
. .
2-13
unit
.
Coding
shown
for deflection factor of
100
microvolts
. . . . . .
.
. . . . . . .
3-44
. . . .
2-13 3-35
Idealized
current
waveforms
of
(A)
Row
analog
data
and
(B)
Column
analog
data
. . . . . . . . . . . .
3-45
. . . .
.3-2
3-36
Block
representation of
memory
sequence
in
U3401
. . . . . . . . . . . . . . . . . . . . . . . . . .
3-47
. . . .
.3-9
3-37
Typical
output
waveforms
for
Zeros
Logic
and
. . .
3-11
Memory
stage
operation
(at
pin 7 of
U3401)
. . . . .
3-48
3-38
Readout
word
relating
10
possible
character
for locations to
the
decimal
point
instructions
that
can
. . .
.
3-12
be
encoded,
and
the
resultant
crt
display
. . . . . . .
3-50
3-39
Flow
chart for
character
generation
by
the
. . . .
3-13
Readout
System
.
.
.
. . . . . . . . . . .
3-51
3-40
Detailed
block
diagram
of
Converter/Rectifiers
. . . .
3-14
circuit
. . . . .
Inverter
. . . . . .
. .
.3-52
r
3-41
(A)
Representation
of
stage
.
Idealized
. .
3-15
waveforms
of
(B)
total
inverter
current,
I
t,
94)
.3-16
(C)
voltage of
CR1234
and
CR1241,
and
(D)
voltage
across
primary
. . . . . . . . . .
3-54
.
. . .
3-17
3-42
Detailed
block
diagram
of the
Low-Voltage
Regulator
circuit
. . . . . . . . .
3-57
. . .
.3-18
3-43
Detailed
block
diagram
of the
Vertical
Amplifier
circuit
. . . .
.
. . .
.3-59
. . . .
3-19
3-44
Detailed
block
diagram
of
the
Horizontal
Amplifier
.
3-61
3-45
Detailed
block
diagram
of the
CRT
Circuit
. . . . . .
3-63
. . . .
3-20 3-46
Detailed
block
diagram
of the
Auto
Focus
Amplifier
circuit
. . . .
.
. . . . . . . . .
3-65
. . . .
3-21
3-47
Detailed
block
diagram
of
the
7834
Storage
System
.3-66
3-48
Bistable
storage
mode
timing
diagram
. . . . . . .
3-68
. . . .
3-22 3-49
Variable
persistence storage
mode
timing
diagram
.
.3-69
3-50
Bistable
fast
storage
mode
timing
diagram
. . . . . . .
3-70
.
3-22
3-51
Variable
persistence
fast
mode
timing
diagram
. . . .
3-71
ealized
4-1
Color
code
for
resistors
and
capacitors
. . . . . . . . .
.44
. . .
3-23
4-2
Orientation
of
multi-connector
holders
. . . . . . .
.4-5
ng
4-3
Current
sensing
waveform
at
R1287
showing
:
. . . .
3-24
A
.
Power
supplies
not
in
current
limit
operation
.
B
.
Power
supplies
in
current
limit
operation
. . . . . .
.4-9
. . .
3-25
4-4
Typical
waveforms
on
C1216
and
C1217
with
the
line
voltage
set to
about
20
V
. .
.
. . . . . . .
4-10
ter
4-5
Current
waveform
at
T1230
showing
burst
operation
.
.
. .
3-26
at line
voltage of
about
60
V
. . . . . . . . . . . .
4-11
. . . .
3-27
4-6
Current
waveform
at
T1230
for
normal
inverter
. . . .
3-28
operation
at line
voltage of
115
V
. . . . . . .
4-11
4-7
Waveform
at
TP1234
on
the
Power-Supply
Inverter
. . . .
3-28
board
with
the
line
voltage at
about
20
V
. . . . . . .
4-11
r
4-8 Disassembly
and
assembly
of
Display
and
. . .
.3-30
Acquisition
units
. . . . . . . . . . . . . . . . .
. .
4-14
r
4-9
Power-supply
unit
securing
screws
. . . . . . . .
4-15
. . .
.3-32
4-10
Location
of
line
storage
capacitor
screws
used
for
manually
discharging
C1216
and
C1217
. . . . . . . .
4-15
. .
.3-33
4-11
Location
of securing
screws
for
the
Main
ng
Interface
board
. . . . . . . . . . . . . . . .
4-18
. . . .
3-35
4-12
Correct
placement
of
power
transistor
and
mount-
ing
hardware
on
rear
heatsink
. . . . . . . . . . . . . .
4-22
. . . .
3-36
4-13
Semiconductor
lead
configurations
. . . . . . . . . . .
4-25
4-14
Coaxial
end-lead
connector
assembly
.
. . . . . . .
4-26
4-15
Exploded
view
of
circuit-board
pin
and
ferrule
. . .
.
4-26
. . . .
3-37 4-16
Removal
procedure
for
pushbutton
switches
. . . .
4-27
. . . .
3-38
5-1
Typical display
when
checking
X-Y
compensation
. .
5-23
. . . .
3-40
5-2
Readout
display
with
Q3416
removed
. . . . . . . . .
5-29
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