Section
3-AA
501
THEORY OF OPERATION
l
ntroduction
CR1520 through CR1626. When the post attenuator
voltage on any scale exceeds about
i10 V, one set of
Refer to the block diagram
located in the foldout Pages
clampdiodes turns on to limit thevoltage at U1420Aand B.
of this manual for a brief description and overall
viewof the
~h~
effect
of
the
nonlinear capacitance
of
clamp diodes
AA 501 operation. A detailed circuit description follows.
CR1620, CR1621,
CR1624
and
CR1625
is eliminated by
maintaining a constant voltage across the diodes via a
bootstrap arrangement.
Input Amplifier
The input amplifier is designed for low noise and
distortion. 'The input is differential with single-ended
The input signal is buffered by low noise amplifiers
output. This circuit provides good common mode rejec-
U1520Aand U1420B. On the 0 dBthrough 40 dBattenua-
tion for suppression of ground loop currents and other
tion ranges, these buffers provide unity gain. Relays
unwanted signals which may be present on both input
K1410 and K1411 change the gain to +20 dB or $10 dB,
leads.
'The input stage is protected to withstand at least
respectively, by adding resistors
R1420D or R1420E.
200 V rms on any input range.
Capacitors
C1423 and C1520 provide frequency compen-
sation.
-The input amplifier gain is set by the logic circuitry at
0 dB (unity),
+
10 dB or
+
20 dB. The logic circuitry controls
the gain so that the signal voltage at the output of the input
amplifier remains between 0.75 V and 3.0 V rms. An
atten-
uator, prior to the amplifier, additionally provides gain
settings from
-
10 dB to -40 dB in 10 dB steps. The actual
gain or attenuation selected depends on the input voltage
level (or the setting of the INPUT LEVEL RANGE switch if
not in AUTO RANGE). A full scale reading of 200 V corre-
sponds to 40 dB of attenuation and 2 V full scale for unity
gain.
-The input signal, from the front panel connections or
the rear interface input (selected by SOURCE switch
S1531) enters the input amplifier through P1620/J1620.
Each input is ac coupled through C1630 or C1631. The
signal then passes to the differential input attenuator
hybrid,
R1510. These resistors are laser trimmed and
ratioed to maintain gain accuracy and good common
mode rejection. Relays
K1412, K1510, K1511, K1512, and
K1610 select attenuation from 0 dB (unity gain) to40 dB,
respectively in 10 dB steps. Frequency compensation of
the attenuator is provided by
C1433 and C1520.
When there is no attenuation (0 dB), DS1520 and
DS1521 limit the input current. The current passing
through the
lamps warms their filaments, increasing their
resistance from a fairly low value.
Theselamps can handle
120
Vac indefinitely and 200 Vac for at least 30 minutes. If
the AA 501 is subjected to greater overloads in the
0 dB
attenuator position, the lamps act as fuses to prevent
damage to the input circuitry. When any attenuation other
than
0 dB is selected, the resistance in the hybrid network
provides current limiting. The inputs are clamped by
Zener diodes
VR1620 and VR1621 through eight diodes,
The buffer outputs are combined into a single-ended out-
put signal by
U1432 (gain=1.5). The output of U1432 pin
6
is ac coupled by C1421 to remove any dc offsets caused by
U1420A, B and U1432. This signal is then routed to the
automatic gain control circuitry
(agc) and input amplifier lev-
el detector.
The gains of the combining stage and the buffers are
controlled by hybrid resistor
R1420. These resistors are
laser trimmed and ratioed to insure gain accuracy and
good common mode rejection.
The signal level at the output of the input amplifier is
detected by active rectifier
U1320 in conjunction with
CR1330 and CR1331. This full wave rectified signal is
filtered by
U1330A with C1420 and routed to the logic
circuitry through
J1500, pin 1. Recovery from overload is
provided by
VR1320. Resistor R1322 sets t he filter gain so
that,with2VintotheAA501 inputonthe2Vscale(3Vat
pin 6 of U1432) the output at pin 1 of U1330A is 6 Vdc.
The gain
settjng relays K1410through K161Oaredriven
by transistors Q1400 through Ql600. Control signalsfrom
the logic circuitry enter the input board through
P1500-
J1500, pins 2through
9,
with one line at atime high (about
1-12 V). This logic high at the base of atransistorturnsthe
transistor on and closes the relay. When either
0 dB,
$10 dB or +20 dB (pins 6, 7 or
8)
is activated, Q1402, is
also activated closing
K1412. l n AUTORANGE, the logic
circuitry selects the proper input attenuation or gain to
maintain 0.75 V to 3.0 V at
U1432 pin 6 for inputs greater
than about 50
mV. Below 50 mVthe rangeis0.3 Vto 3.0 V.
REV
JUN
1981
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