Theory of Operation-AA 501
dB Ratio Circuitry
0
The dB ratio circuitry allows selection of any input
voltage as
0 dB. This is accomplished by adding a dc
offset voltagefrom pin 150f
R1333topin9of U1313C. This
causes
0 Vat pin
8
of U1313C at thedesired AA 501 input
voltage.
Amplifiers
U1331 C and D with resistor network R1333
form a digital to analog converter which supplies the dc
offset to the input of
U1313C. This converter is driven by
an 11 bit binary counter composed of
U1321 and U1332.
This counter is controlled by dual flip-flop U1531 B which
is supplied with a clock signal from the gated oscillator
corpposed of U1431A and B.
When the dB ratio button is pushed (grounded) a
debounce circuit composed of U1431 C and D causes pin 3
of
U1531A to go high. A short time later, determined by
R1441 and C1445, pin 4 of U1531A goes high terminating
the high at pin 1. A positive pulse appears at
U1531 pin 1,
resetting counters
U1321 and U1332 and flip-flop U1531B.
This allows the oscillator to start. The oscillator in-
crements the counters changing the voltage offset. When
the0 dB reference button is pushed the counter starts with
the most negative voltage offset and increments in the
positive direction. The output of
U1313C connects to
comparator
U1331B. When the output of U1313C is 0 V,
U1331B pin 7 goes high, causing U1531B pin 12 to go low
at the next clock pulse. This action stops the oscillator.
Future
dBr readings are referenced to this voltage. Pin 1 of
U1331A goes positive a short time before U1331B pin
7.
This switches the oscillator ot a lower frequency through
Q1447 and C1433 to prevent the circuits from
overshooting the correct value.
6
V
Reference
0
The most significant LED module, DS1022, is con-
trolled by
U1201D and 01201. This digit displays blank. 1
or
0. The 0 is displayed only in the 0.2% distortion range.
If a decimal point is needed in LED display
DS1020,
pin
2 of U1201A is low. This assures that pin 11 of U1201D
is
also low and illuminates the two segments comprising the
one (1) in the most significant digit module,
DS1022. Pin
19 of
U1111 is high when aoisrequired and lowwhen a 1 is
required. The one is changed to a zero by illuminating an
additional four segments of
OS1022. The minus signto the
left of the most significant digit module is used only in the
dB mode.
Q1210 prevents the minus sign from il-
luminating in any other mode.
The ten operational amplifiers,
U1030A, B, U1130 and
U1230 comprise the drivers for the bar graph display. The
analog signal from the dB converter is applied to the
negative inputs of these amplifiers. The input resistance
dividers areselected
sothat only one operational amplifier
at a time is operating in the linear region. There is
approximately 2.5 dB between each segment, with a slight
overlap from one segment to the next.
Display Board
6
The four LED digit display modules and the sign
module are illuminated by lowering the cathode voltages.
The display module anodes and the state
LEDs are
operated from
t
5 V.
Pins 11 through 20 of DS1010, the bar graph display.
are connected to -5 V. Pins 1 through 10 are driven by
operational amplifiers in conformance with the
anlog
signal strength.
Logic Circuitry
@
@
@
The input sianals to the logic section come from the
A
6 V reference voltage to the
dB
converter, offset
front
switches, the
inp$ stage level detector, and
generator,
dBr section, and dvm is provided by U1313A
the distortion amplifier level detector. The logic circuitry
and
VR1406. controls the gain of the input stage and distortion
amplifier, the dB offset generator, location of the decimal
points and the function annunicator LEDs.
The dvm section accepts the dc voltage from the dB
converter or directly from the ac to dc converter and drives
the digital display. The dvm input is proportional to the
input signal voltage, the percent distortion or the log (dB)
of the selected function. An
LSI
analog todigital converter
with display drivers.
U1111, drives the respective
segments in LED display. Overrangeindication issupplied
internally in
U1111. Reference voltage adjustment for the
correct full scale reading is provided by
R1218. Other
external components support the internal
operation of
U1111.
Schematic 10 shows the logic switching circuitry.
On schematic 11 a presettable up-down counter,
U1031, controls and gain of theinput stage. In the manual
ranges, the preset inputs are enabled by S1521-4. The
proper input level range signals are supplied by
51521-1,
2,
and 3. In the auto range position, the counter accepts
clock inputs from level comparators
U1221A and B. These
signals pass from
U1031 to U1011. They are decoded in
U1011, a bcd to decimal decoder, to drive theinput stage
gain control lines.
Scans
by
ARTEK
MEDU
-
To Next Page
Loading...
Need help?
General
