Specifications
Table 28: Trigger Inputs (cont.)
Characteristics Description
Input voltage minimum amplitude 0.5 V
p-p
Threshold control
Range –5.0 V to 5.0 V.
Resolution 0.1 V
Accuracy
± 5% of setting + 0.1 V.
Minimum pulse width 20 ns
Delay to analog output
The DAC sampling clock frequency is displayed on the clock settings tab when the external
clock output is enabled.
Asynchronous trigger mode
8760/ fclk +68 ns ± 20 ns.
(1.820 μsat5GS/s)
(3.572 μsat5GS/s)
fclk is the frequency of the DAC sampling clock. The DAC sampling clock frequency is
displayed on the clock settings tab when the external clock output is enabled.
Synchronous trigger mode 8275 / fclk + 30 ns ±20 ns
(1.685 μs at 5 GS/s.)
(3.340 μs at 2 .5 GS/s.)
fclk is the frequency of the DAC sampling clock. The DAC sampling clock frequency is
displayed on the clock settings tab w hen the external clock output is enabled.
Hold off
>2 μs
Trigger hold off is the amount of delay required at the end of a waveform before another trigger
pulse c an be processed.
Jitter, asynchronous mode
The asynchronous jitter performance is directly proportional the frequency o f the DA C sampling
clock. The DAC sampling clock frequency is displayed on the clock settings tab when the
external clock output is enabled.
1kΩ selected 440 ps
p-p
for 2.5 GHz DAC sampling clock.
240 ps
p-p
for 5 GHz DAC sampling clock.
50 Ω selected 420 ps
p-p
,24ps
rms
for 2.5 GHz DAC sampling clock.
220 ps
p-p
,14ps
rms
for 5 GHz DAC sampling clock.
Jitter, synchronous mode
Trigger synchronized to
Internal or Ext C lock
300 fs
rms
Trigger synchronized to
Variable Reference
400 fs
rms
Trigger synchronized to Fixed
10 MHz Reference
1.7 ps
rms
AWG5200 Series Technical Reference 19