Table of Contents
List of Tables
Table 1: Run mode ................................................................................................. 2
Table 2: Arbitrary waveform...................................................................................... 2
Table 3: Real time digital signal processing..................................................................... 3
Table 4: Sequencer ................................................................................................. 3
Table 5: Sample clock generator.................................................................................. 4
Table 6: Analog output skew...................................................................................... 4
Table 7: Signal output characteristics ............................................................................ 5
Table 8: Harmonic distortion (DC High
BW output path).................................................... 11
Table 9: Harmonic distortion (DC High Voltage output path)................................................ 11
Table 10: Harmonic distortion (AC Direct output path) ...................................................... 12
Table 11: Harmonic distortion (AC Amplified output path).................................................. 13
Table 12: SFDR operating at 2.5 GS/s (DC High Bandwidth, 500 mV
pp
) .................................. 13
Table 13: SFDR operating at 5 GS/s (DC High B andwidth, 500 mV
pp
)..................................... 13
Table 14: SFDR operating at 10 GS/s (DC High Bandwidth, 500 mV
pp
)................................... 14
Table 15: SFDR operating at 2.5 GS/s (AC Direct Out) ...................................................... 14
Table 16: SFDR operating at 5 GS/s (AC Direct Out) ........................................................ 14
Table 17: SFDR operating at 10 GS/s (AC Direct Out)....................................................... 15
Table 18: Phase noise operating at 2.5 GS/s.................................................................... 15
Table 19: Phase noise operating at 5.0 GS/s or 10 GS/s with DDR enabled................................ 15
Table 20: Marker outputs......................................................................................... 15
Table 21: 10 MHz Ref Out (reference output) ................................................................. 16
Table 22: Ref In (reference input) ............................................................................... 17
Table 23: Clock Out............................................................................................... 17
Table 24: Clock In................................................................................................. 17
Table 25: Sync In.................................................................................................. 18
Table 26: Sync Out................................................................................................ 18
Table 27: Sync Cloc
k Out ........................................................................................ 18
Table 28: Trigger Inputs .......................................................................................... 18
Table 29: Pattern Jump In connector ............................................................................ 20
Table 30: Auxiliary Outputs (Flags)............... .. ...................................... ...................... 21
Table 31: Computer system ...................................................................................... 21
Table 32: Display.................................................................................................. 22
Table 33: Power supply........................................................................................... 22
Table 34: Mechanical characteristics............................................................................ 22
Table 35: Environmental characteristics ........................................................................ 24
Table 36: Required equipment for the functional test ......................................................... 30
Table 37: Required equipment for performance tests ......................................................... 42
Table 38: Analog amplitude accuracy (DC High BW output path) .......................... ................ 46
AWG5200 Series Te chnical Reference iii