TeleChips TCC8900 - Figure 14. Circuit of Hdmi Edid with Chipset (Sv1.0); Figure 15. Circuit of Hdmi Edid with the Fet (Sv1.1)

TCC8900 TCC8900_DEMO_AM_2747_V1.1 July, 31, 2009
Board Guide TCC8900 DEMO BOARD REVISIONS (V1.1)
Preliminary 3-20
R33 0
R32 0
C136
0.01uF
SDA1
TC_SDA
R29
0
C137
0.01uF
DGND
HDMI_SCL
HDMI_SDA
R2610K R2710K
DGND
R2810K
HDMI_PWR
SCL0
SDA0
U2
PCA9512ADP
VCC2
1
SCLOUT
2
SCLIN
3
GND
4
VCC
8
SDAOUT
7
SDAIN
6
ACC
5
R38 DNP(0)
DGND
TC_SCL
SCL1
R35 DNP(0)
8900_GPA
Figure 14. Circuit of HDMI EDID with Chipset (SV1.0)
R86 0
R32 0
SDA1
8900_GPA
8900_GPA
Q2
IRLML2502
1
3 2
R83
1K
R84
2.2K
R80
1K
R82
2.2K
R81
2.2K
Q1
IRLML2502
1
3 2
HDMI_SDA
HDMI_SCL
R85
2
SDA0
SCL0
HDMI_PWR
R87 DNP(0)
SCL1
R35 DNP(0)
HDMI_PWR
Figure 15. Circuit of HDMI EDID with the FET (SV1.1)