Telit Wireless Solutions LN930-AP - Host Interface Signals Overview

LN930 M.2 Hardware User Guide
1VV0301078 Rev.10 – 2015-11-11
Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved. Page 21 of 88
SMARTi
TM
4G
PMB5740
RD
_
H1
RD_H1X
RD
_
H3
RD
_
H3
X
RD_
M1
RD
_M
1
X
RD_
L
1
RD
_L
1X
RD
_L
2
RD
_L
2
X
RD_
L4
RD_
L4
X
Clock and
Control
DigRF
VBAT
SD2
_1
V
8
AFC_
DAC
REF OSC
XO_
SUP
XO
VCTCXO
Measurement Unit
M1
M2
M3
Battery
RFE_NTC
RFE
_PADCDC_
MI
XOX
Diversity
Receiver
Combined
Receiver
RX_H2
RX
_H
2
X
RX_H3
RX
_
H3
X
RX_H4
RX
_
H4
X
RX
_
M1
RX_M1X
RX_M2
RX_
M
2X
RX
_
L1
RX
_L
1X
RX_L2
RX
_L
2
X
RX_L4
RX_
L
4X
RFFE
RFFE_VIO
RFFE_SDATA
RFFE_
SCLK
Transmitter
TQ
_X
TQ_H
TQ_L
TP_H
TP_L
PA Control
PADACS
PADACF
PADACF_P
FBR
FBR
_RF1
FBR
_RF2
XGOLD
TM
716
B
7
B1
/B
4
Diversity Switch
&
Filter Module
Diversity
Antenna
RFE_RFFE
_VIO
RFE_
RFFE_SDATA
RFE_RFFE
_SCLK
RFE
_RFFE
_VIO
RFE_
RFFE
_SCLK
RFE_RFFE_SDATA
Main Switch
&
Duplexer Module
B7
Duplexer
B
7
Div Filter
B
20 Div Filter
Coupler
Main
Antenna
RFE_RFFE_VIO
RFE_RFFE_SCLK
RFE
_RFFE
_
SDATA
PA
DCDC
RFE_
TQ_H
RFE_
TP_H
RFE_
TP_L
RFE
_TQ_
L
B2/B
25
VBAT
VBAT
VBAT
RFE_VCC
1_ET
RFE_
VDD_
ET
B7 PA
RFE_PADCDC
_MI
SCPA
RD
_M
2
RD
_M
2
X
RD_
L
3
RD_
L
3X
B
20
RX
_
L
3
RX_L3X
B2
/B
25
B3
B
5/B26
B
13/
B17
B
8
B
20 Duplexer
B7
B20
B1
B4
B2/B25
B3
B5/B26
B8
B13/B17
B1
B4
B3
GSM_HB
GSM_LB
B
8
B5/
B26
B20
B17
B13
RFE_PADACS
VBAT
RFFE CONTROL
VBAT
RFE_VBATAMP
Figure 4 Detailed Interconnection of M.2 LTE Modem RF Engine
2.3
Host Interface Signals
This section describes the signals available to the host processor at the 75 pin application
interface. Eight signals are eliminated by the notch on the host connector, leaving 67 usable
signals. A diagram of the M.2 module identifying the 75 pin interface is shown in Figure 5.
Note that the M.2 module has all components mounted on the top side. Odd pin numbers are on the top
side while even pins on the bottom side.