Chapter 5
NIOS Based Example
Codes
his chapter provides several NIOS based examples for users to get started using the
D8M board.
5.1 DE1_SOC and DE2-115 D8M_VIP
Demonstration
This demonstration shows how to implement a D8M on DE1-SoC and DE2-115 Boards.
The Altera VIP (Video Image Processing) suite is used to display image/s on the VGA
monitor. The Nios II processor is used to configure the I2C devices. There is a Camera
IP from Terasic in Qsys, which translates the Bayer pattern from the camera to the
RGB video steam format and feeds it to the Altera VIP. The other IP developed by
Terasic for auto-focus is used to find the optimized focus settings of the user-defined
image area.
◼ Function Block Diagram
DE1_SOC_D8M_VIP reference design is developed based on Altera’s Video and
Image Processing (VIP) suite. The Terasic Camera IP translates the parallel Bayer
pattern data into RGB data to meet the specification of the Altera VIP video streaming.
The Frame Buffer from VIP is used for buffering image data in DDR3 and matching the
frame rate from the Terasic camera IP to the Clock Video Output of VIP. It displays the
final 640x480 RGB frame image on the VGA Monitor. The auto-focus IP by Terasic can
be used to get a better image quality by finding the optimized focus setting.
Figure 5-1 shows the Function block diagram of DE1_SOC_D8M_VIP demonstration.
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