Program biasing current
and load capacitance for
cystal
Register R2[1:0] for
input selection.
Input Configuration
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SNAU244–July 2019
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Modes of Operations
2.1.2 Crystal Input
By default, register "ref_sel" is set to 0 and pin "REFSEL" is pulled low to enable the use of on-board 25-
MHz crystal. The designer can change the input bias current and load capacitance by programming the
registers highlighted in Figure 2-1. Note that the capacitance listed in the software is a single-ended value
at the drain and source. For example, if the load capacitance selected is 9.8 pF, the capacitance is 9.8 pF
at both the source and drain. Crystal vendors typically refer to load capacitance as effective series
capacitance seen by the crystal. So when 9.8 pF is selected, the real load capacitance should be 4.9 pF.
R5 and R12 are placeholders for external capacitors.
Figure 2-1. Input Configuration
2.2 PLL Configuration
On the TICS Pro "PLL" page, the designer can change input doubler/divider, loop filter component values,
charge pump gain, VCO frequency, fractional N divider, as well as prescaler A and B (PSA and PSB)
separately.
2.3 SSC, DCO and ZDM Modes
To configure SSC, DCO and ZDM modes, refer to the descriptions in the data sheet.
2.4 Output Configuration
On the TICS Pro "Outputs" page, the designer can program output channel MUX, integer output divider
values, as well as output format.
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