Texas Instruments Jacinto 7 DRA829 - Page 45

Resource PMIC Delay Diagram Total Delay Rail Name
nRSTOUT_SOC TPS65941213-Q1
0 us H_SOC_PORz_1V8
BUCK3 Monitor TPS65941213-Q1
7200 us mVDD_MCUIO_3V3
LDO3 TPS65941213-Q1
2500 us VDD_DLL_0V8
BUCK123 TPS65941213-Q1 2500 us VDD_CPU(AVS)
BUCK4 TPS65941213-Q1
7200 us VDD_MCU_0V85
BUCK5 TPS65941213-Q1
3000 us VDD_PHY_1V8
LDO2 TPS65941213-Q1 7200 us VDD_MCUIO_1V8
LDO4 TPS65941213-Q1 5200 us VDA_MCU_1V8
LDO1 TPS65941213-Q1 3000 us VDD1_DDR_1V8
GPIO9 TPS65941213-Q1 3500 us EN_MCU3V3IO_LDSW
GPIO3 TPS65941111-Q1 500 us EN_VDDR
BUCK5 TPS65941111-Q1 500 us VDD_RAM_0V85
LDO3 TPS65941111-Q1 500 us VDD_IO_1V8
BUCK1234 TPS65941111-Q1 2500 us VDD_CORE_0V8
LDO4 TPS65941111-Q1 3000 us VDA_PLL_1V8
LDO1 TPS65941111-Q1 3500 us VDD_SD_DV
LDO2 TPS65941111-Q1 3500 us VDD_USB_3V3
GPIO11 TPS65941111-Q1 3500 us EN_3V3IO_LDSW
nRSTOUT TPS65941213-Q1 16200 us H_MCU_PORz_1V8
Figure 6-10. TO_MCU Sequence with I2C_7 low in both PMICs
The last instructions of the TO_MCU sequence also perform writes to the MISC_CTRL and
ENABLE_DRV_STAT registers after the delay defined in the PFSM_DELAY_REG_1.
// TPS65941213
SREG_READ_REG ADDR=0xCD REG=R1
DELAY_SREG R1
// Clear SPMI_LPM_EN and FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xE7
// Set NRSTOUT (MCU_PORZ)
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x01 MASK=0xFE
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUC99 – JANUARY 2022
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Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
45
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