Texas Instruments Jacinto 7 DRA829 - Page 46

Note
After the TO_MCU sequence the MCU is responsible for managing the EN_DRV.
6.3.8 TO_ACTIVE
When a trigger causes the TO_ACTIVE sequence to execute, all rails power up in the recommended power up
sequence as shown in Figure 6-11.
At the beginning of the TO_ACTIVE sequence both PMICs clear SPMI_LP_EN and LPM_EN and set
AMUXOUT_EN and CLKMON_EN.
Resource PMIC Delay Diagram Total Delay Rail Name
nRSTOUT_SOC TPS65941213-Q1
12700 us H_SOC_PORz_1V8
BUCK3 Monitor TPS65941213-Q1
3700 us mVDD_MCUIO_3V3
LDO3 TPS65941213-Q1 2700 us VDD_DLL_0V8
BUCK123 TPS65941213-Q1 2700 us VDD_CPU(AVS)
BUCK4 TPS65941213-Q1 3700 us VDD_MCU_0V85
BUCK5 TPS65941213-Q1 1700 us VDD_PHY_1V8
LDO2 TPS65941213-Q1 3700 us VDD_MCUIO_1V8
LDO4 TPS65941213-Q1 1700 us VDA_MCU_1V8
LDO1 TPS65941213-Q1 1700 us VDD1_DDR_1V8
GPIO9 TPS65941213-Q1 0 us EN_MCU3V3IO_LDSW
GPIO3 TPS65941111-Q1
3700 us EN_VDDR
BUCK5 TPS65941111-Q1
3700 us VDD_RAM_0V85
LDO3 TPS65941111-Q1 3700 us VDD_IO_1V8
BUCK1234 TPS65941111-Q1 2700 us VDD_CORE_0V8
LDO4 TPS65941111-Q1 1700 us VDA_PLL_1V8
LDO1 TPS65941111-Q1 0 us VDD_SD_DV
LDO2 TPS65941111-Q1 0 us VDD_USB_3V3
GPIO11 TPS65941111-Q1 0 us EN_3V3IO_LDSW
nRSTOUT TPS65941213-Q1 12700 us H_MCU_PORz_1V8
Figure 6-11. TO_ACTIVE Sequence
Pre-Configurable Finite State Machine (PFSM) Settings www.ti.com
46 Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
SLVUC99 – JANUARY 2022
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