3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
Revisions Affected: 0, A, B, C
The SDFM clock input (SDx_Cy) directly clocks the SDFM module when there is no GPIO input synchronization.
Any glitches or ringing noise on the SDx_Cy input beyond V
IH
or V
IL
can corrupt the SDFM module, leading to
unpredictable results.
Workarounds:
SDFM GPIO Asynchronous Mode:
Special attention should be taken during board design to ensure a clean and noise-free signal that meets the
SDFM timing requirements. Precautions such as series termination for ringing due to any impedance mismatch
of the clock driver, and spacing of traces from other high-frequency signals are recommended.
SDFM GPIO Qualification (3-sample) Mode:
It is highly recommended that the SDFM GPIO qualification mode be used in noisy conditions. This mode
provides additional protection by filtering both SDx_Cy and SDx_Dy inputs from system noise. Refer to
the "SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window)" table in the
TMS320F2837xD Dual-Core Real-Time Microcontrollers data sheet when using this option.
When a noise event occurs while using the GPIO Qualification mode, there may still be data disturbance, but
it will be proportional to the duration of the noise event and typically filtered by the oversampling of the SDFM
module. Below is a relative listing of each SDFM mode's sensitivity to data variation in the presence of severe
system noise.
• Mode 0: This mode is the best performing mode. It is the recommended mode under noisy conditions.
• Mode 1 and Mode 3: The error in these modes can be twice as large as the error in Mode 0 since each noise
glitch can introduce error for multiple data bits.
• Mode 2: This option is unavailable when using GPIO qualification. This mode is not recommended for either
GPIO ASYNC or GPIO qualification.
3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register
Without Verifying if the XRDY Bit is in its Ready State (1)
Revisions Affected: 0, A, B, C
If the XRDY bit is used to properly gate writes to the DX2/DX1 registers, this condition will not occur.
Per the operation of the McBSP, a write to the DX1 data transmit register will automatically clear the XRDY
bit, indicating a not-ready status. Once this data is transferred to the internal transmit shift register (XSR1), the
McBSP HW will set the XRDY bit, indicating a ready status, and new data can be written to DX2/DX1 data
transmit registers.
If the set and clear of XRDY occur on the same CPU clock cycle, the XRDY bit will remain cleared and the new
data in the DX2/DX1 will not be transmitted.
In this state of XRDY = 0, the McBSP will be in the not-ready status indefinitely.
Any subsequent writes to DX2/DX1 will behave normally and the XRDY bit will function as normal.
Workarounds:
When transmitting multiple words of data using the McBSP module, poll the XRDY bit in the SPCR2 register
before writing new data to the DX2/DX1 registers to prevent overwriting. For those modules that do not have
access to the XRDY bit (such as the DMA controller), the XINT interrupt inside the McBSP module can be
configured to reflect XRDY (through the XINTM bits in SPCR2 register), and this can also be used to gate writes
to the DX2/DX1 registers. This will also ensure that the XRDY bit is not set and cleared on the same CPU cycle,
causing the above “not-ready indefinitely” condition.
If the system allows multiple bus controllers, such as the C28x CPU and the DMA controller, to write to the
DX2/DX1 registers, then the ready state of the XRDY bit should be validated before passing control of the
McBSP to a different bus controller. This will ensure that the state of XRDY is accurate and the simultaneous
set/clear action does not occur.
Silicon Revision C Usage Notes and Advisories www.ti.com
10 TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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