6 Silicon Revision 0 Usage Notes and Advisories
This section lists the usage notes and advisories for this silicon revision.
6.1 Silicon Revision 0 Usage Notes
Silicon revision-applicable usage notes have been found on a later silicon revision. For more details, see Silicon
Revision C Usage Notes.
6.2 Silicon Revision 0 Advisories
Silicon revision-applicable advisories have been found on later silicon revisions. For more details, see Silicon
Revision C Advisories, Silicon Revision B Advisories, and Silicon Revision A Advisories.
Advisory ADC: ADC Linearity Performance
Revisions Affected
0
Details INL/DNL performance does not meet data sheet specifications. For 16-bit mode, typical
performance is: INL = ±12 LSBs, DNL = [+1.5,-1] LSBs. Missing codes are present
every 512 codes, in sets of up to 16 missing codes in a row. For 12-bit mode, typical
performance is: INL = ±4 LSB, DNL = [+1, -1] LSBs. Missing codes are present every
128 codes, in sets of up to 4 missing codes in a row.
Workarounds None
www.ti.com Silicon Revision 0 Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
49
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