5 Silicon Revision A Usage Notes and Advisories
This section lists the usage notes and advisories for this silicon revision.
5.1 Silicon Revision A Usage Notes
Silicon revision-applicable usage notes have been found on a later silicon revision. For more details, see Silicon
Revision C Usage Notes.
5.2 Silicon Revision A Advisories
Silicon revision-applicable advisories have been found on later silicon revisions. For more details, see Silicon
Revision C Advisories and Silicon Revision B Advisories.
Advisory ADC: Functionality of V
REFLO
Pins
Revisions Affected
0, A
Details The V
REFLO
pins on Revision 0 and Revision A silicon are not connected. V
REFLO
functionality for all ADCs is provided by an internal connection to V
SSA
on these revisions.
This may result in increased ADC noise and increased ADC-to-ADC crosstalk.
It is recommended that all V
REFLO
pins be connected to either V
SSA
or to 0-V low
reference voltage for these device revisions. This will allow printed circuit boards to be
compatible with future devices.
Workarounds None
Advisory ADC: Sensitivity to ESD Events
Revisions Affected
0, A
Details These TMX revisions have shown sensitivity to ESD damage when safe handling
procedures are not strictly followed. Specifically, the ADC performance can be degraded
after an ESD event.
Workarounds TI always recommends best practice ESD safe device handling. For these TMX revisions,
extra care should be taken to ensure proper ESD handling procedures are followed (that
is, use ESD mats, wrist-straps, ionizers, and so forth). If ADC performance becomes
degraded, replace the device.
www.ti.com Silicon Revision A Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
43
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