Advisory XRS may Toggle During Power Up
Revisions Affected
0, A, B
Details During device power up, the XRS pin may toggle high prematurely. After the V
DDIO
and
V
DD
supplies reach the recommended operation conditions, the XRS pin behavior will
be per the pin description. This is only an issue with the external state of the XRS pin.
Internally, the device will be held in reset by the POR logic until the supplies are within an
acceptable range and XRS is high.
Workarounds Disregard XRS activity on the board prior to supplies reaching recommended operating
conditions.
Advisory VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ
Revisions Affected
0, A, B
Details During power up of the 3.3-V V
DDIO
, the internal Voltage Regulator (VREG) will be active
until the 1.2-V V
DD
supply reaches approximately 0.7 V. After this time, the VREGENZ pin
tied to V
DDIO
will disable the internal VREG. This will not impact device operation.
Workarounds None
Advisory ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled
Revisions Affected
0, A, B
Details The VCU-II can power up in a state which incorrectly sets the VCU VSTATUS[DIVE] error
bit and, subsequently PIEIFR12[INTx6], when the CPU is released from reset. When the
VCU interrupt enable PIEIER12[INTx6] is enabled for the first time by the application, a
spurious interrupt can occur due to the erroneous pending interrupt.
Workarounds Before enabling VCU interrupt 12.6, execute the following instructions to avoid the
spurious interrupt.
// Clear VCU divide by zero status
asm(" VCLRDIVE");
// Clear PIE interrupt for VCU
PieCtrlRegs.PIEIFR12.bit.INTx6 = 0;
Beginning with revision C silicon, the Boot ROM will perform the above workaround before
branching to the application.
Advisory Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present
Revisions Affected
B
Details The device boot code will attempt to configure the device using X1 as the clock source.
When X1 is not present, the device boot will hang. This advisory applies to any system
which is designed to use the INTOSC as the primary clock source with no clock on X1
during boot. This issue only affects some silicon revision B devices and it will be fixed in
all future silicon revisions.
Workarounds Apply external clock source to X1 on silicon revision B devices, even if using INTOSC as
the application clock source.
Silicon Revision B Usage Notes and Advisories www.ti.com
42 TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
