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1 Usage Notes and Advisories Matrices

Table 1-1 lists all usage notes and the applicable silicon revisions. Table 1-2 lists all advisories, modules

affected, and the applicable silicon revisions.

1.1 Usage Notes Matrix

Table 1-1. Usage Notes Matrix

NUMBER TITLE

SILICON REVISIONS AFFECTED

0 A B C

Section 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write

and Manual CPU Interrupt Mask Clear

Yes Yes Yes Yes

Section 3.1.2 Caution While Using Nested Interrupts Yes Yes Yes Yes

Section 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained Yes Yes Yes Yes

Section 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions Yes Yes Yes Yes

Section 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data

is Written to the DX1 Register Without Verifying if the XRDY Bit is

in its Ready State (1)

Yes Yes Yes Yes

1.2 Advisories Matrix

Table 1-2. Advisories Matrix

MODULE DESCRIPTION

SILICON REVISIONS AFFECTED

0 A B C

Analog Bandgap References Yes Yes Yes Yes

Analog Trim of Some TMX Devices Yes Yes Yes

ADC ADC: ADC Post-Processing Block Limit Compare Yes Yes Yes Yes

ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt

Mode) is not Set

Yes Yes Yes Yes

ADC ADC: ADC Offset Trim in Different Modes Yes Yes Yes Yes

ADC ADC: DMA Read of Stale Result Yes Yes Yes Yes

ADC ADC: Random Conversion Errors Yes Yes Yes

ADC ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital

Compare Submodule

Yes Yes Yes

ADC ADC: 12-Bit Switch Resistance Yes Yes Yes

ADC ADC: 12-Bit Input Capacitance When Switching Channel Groups Yes Yes Yes

ADC ADC: Functionality of V

REFLO

Pins Yes Yes

ADC ADC: Sensitivity to ESD Events Yes Yes

ADC ADC: ADC Input Multiplexer Connection at Beginning of Acquisition

Window

Yes Yes

ADC ADC: ADC Sparkle Codes Yes Yes

ADC ADC: ADC Linearity Performance Yes

XRS may Toggle During Power Up Yes Yes Yes

CLB CLB: Back-to-Back PUSH or PULL Instructions With More Than

One Active High-Level Controller (HLC) Channel is Not Supported

Yes Yes Yes Yes

USB USB: USB DMA Event Triggers are not Supported Yes Yes Yes Yes

VREG VREG: VREG Will be Enabled During Power Up Irrespective of

VREGENZ

Yes Yes Yes

Flash Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-

Bit-Error ISR

Yes Yes Yes Yes

Flash Flash: Minimum Programming Word Size Yes Yes Yes Yes

Flash Flash: Reset of CPU2 While it has Pump Ownership Can Cause

Erroneous Flash Reads From CPU1

Yes Yes

ePIE ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First

Enabled

Yes Yes Yes

www.ti.com Usage Notes and Advisories Matrices

SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023

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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon

Revisions C, B, A, 0)

Brand	Texas Instruments
Model	TMS320F2837 D Series
Category	Microcontrollers
Language	English

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