Advisory Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR
Revisions Affected
0, A, B, C
Details When a single-bit ECC error is detected, the CPU executes the single-bit-error interrupt
service routine (ISR). When the ISR returns, the same instruction that caused the first
error is fetched again. If the ECC error threshold (ERR_THRESHOLD.THRESHOLD)
is 0, then the same error is detected and another ISR is executed. This continues in an
endless loop. This sequence of events only occurs if the error is caused by a program
fetch operation, not a data read.
Workarounds Set the error threshold bit-field (ERR_THRESHOLD.THRESHOLD) to a value greater
than or equal to 1. Note that the default value of the threshold bit-field is 0.
Advisory Flash: Minimum Programming Word Size
Revisions Affected
0, A, B, C
Details The Main Array flash programming must be aligned to 64-bit address boundaries and
each 64-bit word may only be programmed once per write/erase cycle.
Applications using Fapi_issueProgrammingCommand() in Fapi_AutoEccGeneration or
Fapi_DataAndEcc modes are implicitly performing 64-bit programming since ECC is
programmed for each 64 bits. Applications using Fapi_DataOnly mode with fewer than
64 bits may be impacted by this advisory.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each
128-bit word may only be programmed once. The exceptions are:
1. The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP
should be programmed together, and may be programmed 1 bit at a time as required
by the DCSM operation.
2. The DCSM Zx-LINKPOINTER3 value in the DCSM OTP may be programmed 1 bit at
a time as required by the DCSM operation.
Workarounds All applications should follow the restrictions outlined in this advisory. Contact TI for
devices already in production which violate this advisory.
www.ti.com Silicon Revision C Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
15
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