Advisory Flash: Reset of CPU2 While it has Pump Ownership Can Cause Erroneous Flash
Reads From CPU1
Revisions Affected
0, A
Details If the CPU2 Subsystem is reset while it owns the flash pump semaphore, then the flash
pump itself will also reset. Since the flash pump is also used by the CPU1 Subsystem,
any instruction fetch or data read from flash by CPU1 will return invalid data. This
will result in a hard fault, incorrect program execution, or an unspecified error in the
application.
This erratum does not apply if the CPU2 Subsystem never writes to the PUMPREQUEST
register to take ownership of the flash pump semaphore.
Workarounds CPU1 must not access flash while CPU2 holds the flash pump semaphore ownership.
The following steps describe how this can be achieved:
1. At application start-up, CPU2 reads the PUMPREQUEST semaphore register. If it is
the owner, CPU2 relinquishes the flash pump semaphore.
2. When CPU2 wants to own the flash pump semaphore, it must notify CPU1 and wait
for an acknowledgement.
3. The CPU1 application branches to RAM and notifies CPU2 that it has done so. Any
data being accessed by CPU1 must also reside in RAM at this time.
4. CPU2 takes ownership of the semaphore.
5. CPU1 will refrain from accessing the flash until CPU2 releases ownership of the flash
pump semaphore.
Advisory CMPSS: CMPIN4N, CMPIN4P, CMPIN5N, and CMPIN5P Not Available
Revisions Affected
0, A
Details The CMPIN4N, CMPIN4P, CMPIN5N, and CMPIN5P functions are not available on the
silicon revisions affected.
Workarounds None
www.ti.com Silicon Revision A Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
45
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