Advisory ADC: ADC Offset Trim in Different Modes
Revisions Affected
0, A, B, C
Details A different offset trim is required when switching between 12-bit and 16-bit resolution and
when switching between single-ended and differential signaling mode.
Workarounds Whenever setting the resolution or signal mode of the ADC, use the “AdcSetMode”
function in C2000Ware. This will ensure the correct trims are loaded into the offset trim
register. Note that on start-up, trims will be loaded for 12-bit, single-ended operation.
Advisory ADC: DMA Read of Stale Result
Revisions Affected
0, A, B, C
Details The ADCINT flag can be set before the ADCRESULT value is latched (see the t
LAT
and t
INT(LATE)
columns in the ADC Timings tables of the TMS320F2837xD Dual-Core
Real-Time Microcontrollers data sheet). The DMA can read the ADCRESULT value as
soon as 3 cycles after the ADCINT trigger is set. As a result, the DMA could read a prior
ADCRESULT value when the user expects the latest result if all of the following are true:
• The ADC is in late interrupt mode.
• The ADC operates in a mode where t
INT(LATE)
occurs 3 or more cycles before t
LAT
(ADCCTL2 [PRESCALE] > 2 for 12-bit mode).
• The DMA is triggered from the ADCINT signal.
• The DMA immediately reads the ADCRESULT value associated with that ADCINT
signal without reading any other values first.
• The DMA was idle when it received the ADCINT trigger.
Only the DMA reads listed above could result in reads of stale data; the following non-
DMA methods will always read the expected data:
• The ADCINT flag triggers a CLA task.
• The ADCINT flag triggers a CPU ISR.
• The CPU polls the ADCINT flag.
Workarounds Trigger two DMA channels from the ADCINT flag. The first channel acts as a dummy
transaction. This will result in enough delay that the second channel will always read the
fresh ADC result.
www.ti.com Silicon Revision C Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
13
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