Advisory (continued) Analog Trim of Some TMX Devices
If the internal oscillator trim contains all zeros, the user can adjust the lowest 10 bits of
the oscillator trim register between 1 (minimum) and 1023 (maximum) while observing the
system clock on the XCLOCKOUT pin.
Advisory ADC: Random Conversion Errors
Revisions Affected
0, A, B
Details The ADC may have errors at a rate as high as 1 in 10
6.5
ADC conversions in 12-bit mode
and as high as 1 in 10
8.75
conversions in 16-bit mode. When a conversion error occurs, it
will be a significant random jump in the digital output of the ADC without a corresponding
change in the ADC input voltage, otherwise known as a “sparkle code”. The magnitude of
this jump will typically be in the range of 20 LSBs to 200 LSBs; however, larger or smaller
jumps may occur.
Workarounds For the revisions affected, the error rate will be lower than 1 error in 10
14.5
ADC
conversions for both 12-bit mode and 16-bit mode when all of the following configurations
are used:
• The S+H duration is at least 320 ns
• ADCCLK is 40 MHz or less
• ADCCLK prescale is a whole number: /1.0, /2.0, /3.0, /4.0, /5.0, /6.0, /7.0, or /8.0
• The value of 0x7000 is written to memory locations 0x0000 743F, 0x0000 74BF,
0x0000 753F, and 0x0000 75BF (writing this value is only valid when the ADCCLK
prescale is a whole number).
Advisory ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule
Revisions Affected
0, A, B
Details The ADCxEVT trigger to the ePWM digital compare submodule may not be detected by
the ePWM.
Workarounds The ADCxEVT can generate an ADCx_EVT interrupt to the PIE. The ISR can be used to
perform the desired task in software.
Advisory ADC: 12-Bit Switch Resistance
Revisions Affected
0, A, B
Details The ADC input model should be used to select the sample-and-hold (S+H) duration for
each ADC input. For the revisions affected, the 12-bit input model under-estimates the
value of the sampling switch resistance (R
on
). A R
on
value of 2 kΩ should be used to
select the S+H duration for these revisions.
Workarounds For the revisions affected, the S+H duration should be chosen to account for the
additional switch resistance.
Silicon Revision B Usage Notes and Advisories www.ti.com
40 TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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