Texas Instruments TMS34010 - Double-Precision Floating-Point Format

Appendix D
0.2 Double-Precision Floating-Point Format
The double precision floating point format supported by the TMS34010 C
floating
point RTS is a 64-bit format: a sign bit. an 11-bit biased exponent, a
52-bit mantissa. The three component fields are positioned in the 64-bit field
format as follows:
6362 5251
o
lsi EXP I
MANTISSA
MSB LSB
Figure 0-2. Double-Precision Floating Point Format
Hence, the sign bit is bit 63 of the 64-bit field, the exponent resides in bits
52 through
62, and the mantissa is in bits 0 through 51 .
Given
an sign bit s, an exponent e, and a mantissa f, then the value V of the
floating point number X=(s,e,f) is as follows:
•
If s = 0, e = 2047, and f = 0, then V = +infinity
• If s = 1, e = 2047, and f = 0, then V = -infinity
• If 0 < e < 2047 and f ¢ 0, then V = (_1)5 2e-1023(.f)
(V = Not Valid if the number X=(s,e,f) is not a normalized floating point
number. See Floating Point Arithmetic, Rounding, and Normalization,
page D-4.)
• If s = 0, e = 0, and f = 0, then V = 0
•
For all other cases, V = Not Valid
Precision in the double- precision format is greater than fifteen decimal digits
and the range
includes the following:
• 1.11254 x 10-
308
to 8.98847 x 10
308
(positive range)
(1.11254
E-308 to 8.98847 E308, in C format)
• -8.98847 x 1 0
308
to -1 .11 254 x 10-
308
( negative range)
( -8.98847
E308 to -1.11254 E-308, in C format)
• 0 (zero)
• + / - infinity
0-3