Texas Instruments TPS65982 - Page 31

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t
f
70 %
30 %
SDA
t
f
70 %
30 %
S
t
r
70 %
30 %
70 %
30 %
t
SCL
HD;DAT
1 / f
1 clock cycle
SCL
st
70 %
30 %
70 %
30 %
t
r
t
cont.
VD;DAT
cont.
SDA
SCL
t
SU;STA
t
HD;STA
Sr
t
SP
t
SU;STO
t
BUF
P S
t
HIGH
9 clock
th
t
HD;STA
t
LOW
70 %
30 %
t
VD;ACK
9 clock
th
t
SU;DAT
Figure 8-4. I
2
C Slave Interface Timing
Valid Data
Valid Data
t
dact
t
per
t
dpico
t
dpico
t
whigh
t
wlow
t
supoci
t
hdpoci
t
dinact
SPI_CSZ
SPI_CLK
SPI_PICO
SPI_POCI
Figure 8-5. SPI Controller Timing
Valid Data
Valid Data
SWD_CLK
SWD_DATA (Output)
SWD_DATA (Input)
t
dout
t
per
t
whigh
t
wlow
t
dout
t
suin
t
hdin
Figure 8-6. SWD Timing
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TPS65982
SLVSD02E – MARCH 2015 – REVISED AUGUST 2021
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