u-blox UBX-G7020 - 4.2 Schematic and bill of material design-in checklist; 4.3 Layout design-in checklist

UBX-G7020 - Hardware Integration Manual
Design-in Checklists
GPS.G7-HW-10003 Objective Specification Page 58 of 74
4.2 Schematic and bill of material design-in checklist
Power Supply:
 Low impedance, low ripple supply voltage is supplied to VDD_IO and V_CORE (<< 1 Ohm): Sections
2.1.2.1 and 2.1.2.2.
 Backup supply used or V_BCKP connected to VDD_IO: Section 2.1.2.3.
 Ferrite bead used to separate VDD_ANA and VDD_LNA from LDO_RF_OUT supply: Section 2.1.2.4.
 VDD_USB connected to GND if USB interface is not used: Section 2.7.
 Capacitor at LDO_X_OUT to GND has to be in place for crystal and TCXO designs: Section 2.4.
 System power supply is capable of delivering maximum current as specified in the UBX-G7020-Kx Data
Sheet [1] and UBX-G7020-CT Data Sheet [2].
Interfaces:
 If SQI flash is used, part number is listed in section 3.4.
 Interface lines are protected from electromagnetic interference: Section 2.2.3.4
 A second serial interface is available for debugging at test-points: Section 2.2.3.
System functions:
 Real-Time clock circuit is present or not needed: Section 2.5.
 SAFEBOOT_N pin is accessible at a test-point: Section 2.2.6.
 Configuration pins (PIO0 to PIO5) are set as required by application (DCDC converter, LDO_X_OUT
voltage): Section 2.2.2.
 SQI flash size and type are chosen correctly regarding application, means use of SQI flash (firmware
and/or logging): Section 3.4.
RF section:
 Interference, ESD and RF power maximum rating issues have been addressed and the appropriate input
circuit has been selected: Section 2.6.
 Use of additional external LNA has been evaluated based on required system performance: Section
2.6.2.2.
 A GPS/GNSS grade TCXO or crystal has been selected: Section 2.4, Table 13 and Table 15.
 Only COG, low tolerance capacitors are used in crystal circuit: Section 2.4.4.
4.3 Layout design-in checklist
General:
 Footprint for the u-blox 7 UBX-G7020 chip has been properly designed: Section 2.9.2
 RTC Crystal oscillator section is shielded by a GND guard ring: Section 2.9.1
 A proper GND concept is in place and solid GND plane and plenty of vias are being used for good RF
GND connections: Section 2.9.1
 Power supply lines to V_CORE (or V_DCDC_IN in case of DCDC converter used) are wide and short and
have plenty of vias to ensure low impedance: Section 2.1.2.1.
 In case feed-thru capacitors are being used, these are well connected to solid GND plane using plenty of
vias.
 DCDC converter capacitor is well connected to GND and line from V_DCDC_OUT to V_VORE are short
and wide.
RF Section:
 Crystal and/or TCXO are isolated from thermal gradients and air convection: Section 2.4 and 2.9.1
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