SARA-G450 - System integration manual 
UBX-18046432 - R08  Design-in  Page 109 of 143 
C1-Public     
2.7.1.2  Guidelines for microphone and loudspeaker connection circuit design 
Figure 70 shows an  application circuit for the analog audio interface, connecting a 2.2 kΩ electret 
microphone and an 8 Ω or 4 Ω loudspeaker: 
  External microphone can be connected to the uplink path of the module, since the module provides 
supply and reference as well as differential signal input for the external microphone. 
  Using an 8 Ω or 4 Ω loudspeaker, an external audio amplifier must be provided on the application 
board to amplify the low power audio signal provided by the downlink path of the module, so that 
the external audio amplifier will drive the 8 Ω or 4 Ω loudspeaker, since differential analog audio 
output of the module is not able to directly drive loads with such a resistance rating. 
As in the example circuit in Figure 70, follow the general guidelines for the design of an analog audio 
circuit: 
  Provide an appropriate supply to the used electret microphone, providing a clean connection from 
the MIC_BIAS supply output to the microphone. It is suggested to implement a bridge: 
o  The electret microphone, with its nominal intrinsic resistance value, represents one resistor of 
the bridge. 
o  To achieve  good  supply  noise  rejection,  the  ratio  of  the  two resistances  in  one  leg  (R2/R3) 
should be equal to the ratio of the two resistances in the other leg (R4/MIC), i.e. R2 must be 
equal to R4 (e.g. 2.2 kΩ) and R3 must be equal to the microphone nominal intrinsic resistance 
value (e.g. 2.2 kΩ). 
  Provide a series resistor at the MIC_BIAS supply output and then mount a good bypass capacitor 
to provide additional supply noise filtering, as the R1 series resistor (2.2 kΩ) and the C1 bypass 
capacitor (10 µF). 
  Do not place  a  bypass  capacitor directly  at  the  MIC_BIAS  supply  output,  since  an  appropriate 
internal  bypass  capacitor  is  already  provided  to  guarantee  stable  operation  of  the  internal 
regulator. 
  Connect the reference of the microphone circuit to the MIC_GND pin of the module as a sense line. 
  Provide an appropriate series capacitor  at  both  MIC_P  and  MIC_N analog uplink  inputs  for  DC 
blocking  (as  the  C2  and  C3  100  nF  Murata  GRM155R71C104K  capacitors  in  Figure  70).  This 
provides  a  high-pass  filter for  the  microphone  DC bias  with a  corresponding  cut-off  frequency 
according to the value of the resistors of the microphone supply circuit. Then connect the signal 
lines to the microphone. 
  Provide  suitable  parts  on  each  line  connected  to  the  external  microphone  as  noise  and  EMI 
improvements,  to  minimize RF coupling  and  TDMA noise, according  to the custom application 
requirements: 
o  Mount an  82  nH  series  inductor  with  a  Self-Resonance  Frequency  ~1  GHz  (e.g.  the  Murata 
LQG15HS82NJ02) on each microphone line (L1 and L2 inductors in Figure 70). 
o  Mount a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) from each microphone line to 
solid ground plane (C4 and C5 capacitors in Figure 70). 
  Use a microphone designed for GSM applications, which typically has an internal built-in bypass 
capacitor. 
  Provide  a  47  nF  series  capacitor  at  both  SPK_P  and  SPK_N  analog  downlink  outputs  for  DC 
blocking (C8 and C9 Murata GRM155R71C473K capacitors in Figure 70). Then connect the lines to 
the differential input of an appropriate external audio amplifier, differential output which must be 
connected to the 8 Ω or 4 Ω loudspeaker (see the Analog Devices SSM2305CPZ filter-less mono 
2.8 W class-D audio amplifier in the circuit described in Figure 70). 
  Provide  suitable  parts  on  each  line  connected  to  the  external  loudspeaker  as  noise  and  EMI 
improvements,  to  minimize  RF  coupling,  according  to  the  EMC  requirements  of  the  custom 
application: 
o  Mount a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) from each loudspeaker line 
to solid ground plane (C6 and C7 capacitors in Figure 70).