SARA-G450 - System integration manual
UBX-18046432 - R08 Appendix Page 136 of 143
C1-Public
A.3 Schematic for SARA modules integration
Figure 78 shows an example of a simple schematic diagram where a SARA-N2, SARA-N3, SARA-R4,
SARA-R5, SARA-G3, SARA-G4 and/or SARA-U2 module is integrated in the same application board,
using the main available interfaces and functions of the modules.
The different mounting options for the external parts are highlighted in different colors as described
in the legend, according to the interfaces supported by the each module, and related characteristics.
In the simple schematic diagram shown in Figure 78, the VCC supply of the SARA modules is provided
by a suitable supply source, at 3.6 V nominal voltage, not illustrated in the diagram. The application
processor controls the VCC supply of the modules by means of a high-side switch. Proper bypass
capacitors and EMI filter parts are placed close to the VCC input pins of the modules.
While selecting the supply source for SARA cellular modules, consider with adequate safe design
margin the maximum current consumption of each SARA cellular module (see the related data sheet
[1], [2], [3], [4], [5], [6], [7]), as it reflects the RATs supported. For additional specific design guidelines,
see the VCC interface sections in related system integration manual [8], [9], [10], [11].
The switch-on sequence of SARA-N2, SARA-R510M8S, SARA-G3 and SARA-U2 starts by applying a
valid VCC supply.
Instead, SARA-N3, SARA-R4, SARA-R510S and SARA-G4 modules continue to be switched off even
after a valid VCC supply has been applied: the PWR_ON / PWR_CTRL line has to be properly toggled,
with valid VCC supply present, to start the switch-on sequence of these modules.
The application processor is connected to the SARA modules over main UART interface in the simple
schematic diagram illustrated in Figure 78.
The design is implemented with the UART interface configured at the same voltage level on both sides
(application processor and SARA module), without using voltage translators, as it is recommended in
order to minimize any possible leakage and benefit from the extremely low current consumption of
the u-blox LPWA modules, in particular in deep-sleep power saving mode.
Thus, the supply level of the application processor is selected to properly set its UART voltage level:
at the VCC level of the module (3.6 V nominal), in case of SARA-N2
at the V_INT level of the module (2.8 V nominal, with VSEL unconnected), in case of SARA-N3
at the V_INT level of the module (3.0 V nominal, with VSEL unconnected), in case of SARA-G4
at the V_INT level of the module (1.8 V nominal), for all the other SARA modules
The TXD and RXD data lines, supported by all the SARA modules for AT and data communication, are
directly connected with the application processors. For additional specific design guidelines, see the
UART sections in the related system integration manual [8], [9], [10], [11].
The RTS, CTS and RI lines are connected with the application processors by 0 Ω jumpers for all the
SARA modules except the SARA-N2 series, which does not support hardware flow control
functionality and instead supports RI functionality over the CTS output pin.
The other UART lines are not implemented in the simple example of design shown in Figure 78, and
the DTR input is grounded as required to have URCs and the greeting text sent by SARA-R4, SARA-R5
and SARA-U2 modules.
The application processor controls the PWR_ON / PWR_CTRL line by means of an open drain driver in
the circuit illustrated in Figure 78, with an external pull-up to V_BCKP for SARA-G3 and SARA-U2
modules. The whole circuit need not be populated for SARA-N2 modules, which do not provide
PWR_ON / PWR_CTRL input.
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