SARA-G450 - System integration manual
UBX-18046432 - R08 Design-in Page 116 of 143
C1-Public
2.13 Design-in checklist
2.13.1 Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at the VCC pins above the minimum operating range
limit.
DC supply must be capable of providing 1.9 A current pulses, providing a voltage at VCC pins above
the minimum operating range limit and with a maximum 400 mV voltage drop from the nominal
value.
VCC supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors,
in particular if the application device integrates an internal antenna.
Do not apply loads which might exceed the limit for maximum available current from the V_INT
supply.
Check if VSEL is properly connected to GND or left unconnected.
Check that the voltage level of any connected pin does not exceed the relative operating range.
Capacitance and series resistance must be limited on each SIM signal to match the SIM
specifications.
Insert the suggested capacitors on each SIM signal, and low capacitance ESD protections if
accessible.
Check UART signals direction, as signal names follow the ITU-T V.24 recommendation [19].
Provide accessible Test-Points directly connected to the following pins: V_INT, PWR_ON,
PWR_OFF, TXD_FT, and RXD_FT for module FW upgrade and/or for diagnostic purpose.
Add an appropriate pull-up resistor (e.g. 4.7 kΩ) to V_INT or another suitable supply on each DDC
(I2C) interface line, if the interface is used.
Capacitance and series resistance must be limited on each line of the DDC (I2C) interface.
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor
on the board in series to the GPIO when those are used to drive LEDs.
Insert the suggested passive filtering parts on each analog audio line used.
Provide the correct precautions for ESD immunity as required on the application board.
Any external signal connected to any generic digital interface pin must be tri-stated or set low
when the module is in power-off mode and during the module power-on sequence (at least until
the settling of the V_INT supply output of the module to the configured 1.8 V / 3 V value), to avoid
latch-up of circuits and let a clean boot of the module.
All unused pins can be left unconnected.
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