Xilinx Alveo U250 - Page 8

• Memory (four independent dual-rank DDR4 interfaces)
○ 64 gigabyte (GB) DDR4 memory
○ 4x DDR4 16 GB, 2400 mega-transfers per second (MT/s), 64-bit with error correcng code
(ECC) DIMM
○ x4/x8 unregistered dual inline memory module (UDIMM) support
• Conguraon opons
○
1 gigabit (Gb) Quad Serial Peripheral Interface (SPI) ash memory
○ Micro-AB universal serial bus (USB) JTAG conguraon port
• 16-lane PCI Express
• Two QSFP28 connectors 100G interfaces
• USB-to-UART FT4232HQ bridge with Micro-AB USB connector
• PCIe Integrated Endpoint block connecvity
○ Gen1, 2, or 3 up to x16
• I2C bus
• Status LEDs
• Power management with system management bus (SMBus) voltage, current, and temperature
monitoring
• Dynamic power sourcing based on external power supplied
• 65W PCIe slot funconal with PCIe slot power only
• 150 W PCIe slot funconal with 110 A max V
CCINT
current PCIe slot power and 6-pin PCIe
AUX power cable connected
• 225 W PCIe slot funconal with 160 A max V
CCINT
current PCIe slot power and 8-pin PCIe
AUX power cable connected
• Onboard reprogrammable ash conguraon memory
• Front panel JTAG and universal asynchronous receiver-transmier (UART) access through the
USB port
• FPGA congurable over USB/JTAG and Quad SPI conguraon ash memory
Chapter 1: Introduction
UG1289 (v1.1.1) November 20, 2019 www.xilinx.com
Alveo U200 and U250 Accelerator Cards 8
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