Name: Xilinx Artix-7 FPGA AC701
Brand: Xilinx
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12 www.xilinx.com AC701 Getting Started Guide

UG967 (v3.0) July 10, 2013

Basic Hardware Bring-up with Built-In Self-Test

Run the BIST Application

1. Download RDF0220 (AC701 BIST design files) from the web at www.xilinx.com/ac701

under the Docs & Designs tab.

2. Unzip the design files to the C:\ directory.

3. Open a Vivado Tcl shell: Start > All Programs > Xilinx Design Tools >

Vivado 2013.2 > Vivado 2013.2 Tcl Shell

4. Start the installed terminal program.

5. Select Setup > Serial Port… and ensure that the settings match those shown in

Figure 8:

• Baud Rate: 9600

• Data: 8 bit

• Parity: none

• Stop: 1 bit

• Flow control: none

6. In the Vivado Tcl shell, type:

source C:/ac701_bist/ready_for_download/bist_download.tcl

7. Select the desired tests to run and observe the test results (see Figure 9).

X-Ref Target - Figure 8

Figure 8: Serial Port Setup

UG967_08_111412

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Xilinx Artix-7 FPGA AC701 Specifications

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