Xilinx LogiCORE 1000BASE-X - Page 27

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 27
UG155 March 24, 2008
Core Interfaces
R
functionality. For more information, see Chapter 3, “Generating and Customizing the
Core.”
Figure 2-3: Component Pinout Using RocketIO Transceiver
with PCS Management Registers
mdc
mdio_in
gmii_rxd[7:0]
gmii_txd[7:0]
gmii_tx_en
mgt_rx_reset
gmii_tx_er
reset
gmii_rx_dv
gmii_rx_er
GMII
MDIO
phyad[4:0]
gtx_clk
signal_detect
mdio_out
mdio_tri
rxbufstatus[1:0]
rxchariscomma
rxcharisk
RocketIO Interface
gmii_isolate
link_timer_value[8:0]
an_interrupt
Auto_Negotiation
mgt_tx_reset
rxclkcorcnt[2:0]
rxdata[7:0]
rxdisperr
rxnotintable
rxrundisp
txbuferr
userclk
dcm_locked
userclk2
powerdown
txchardispmode
txchardispval
txcharisk
txdata
enablealign
status_vector[4:0]